Interconnect Routing in VLSI

Interconnect Routing in VLSI Glauco Borges Valim dos Santos - FUCAS - GME - II - UFRGS - 2004

Considering two metal layers available for doing that - Metal2 and Metal3 (cells would be using only Poly and Metal 1) a topology for this net could be like this ... met2 met3 via

With the gates the layout would be: met met3 via

The net is now connected INV NOR NANDA NANDB

But notice that a Metal 2 segment overlaps with the INV output, turning it unreachable by other connections INV NOR NANDA NANDB

This in undesirable and is one of the basic routing constraints: do not overlap other nets terminals INV NOR NANDA NANDB

If we change the layers preferred directions the topology goes like this, and the INV output is overlapped by Metal 3, what makes it still available in Metal 2 INV NOR NANDA NANDB

But this time we’ve switched the via witch use to connect the NANDA output to metal 3, for three other vias in the other gates inputs, in order to make them available to the superior metal layer INV NOR NANDA NANDB

Vias are resistive, increasing signal propagation delay and should be avoided. What takes us to another basic routing constraint: to reduce the number of vias INV NOR NANDA NANDB

Now take a look at this alternative topology. Fot this net topology, lower level connections do not overlap each other making them unreachable

And the number of vias is the same of the first case we considered, only four

And also!!! The total wire area is smaller them the previous topologies. Witch means smaller capacitance to be loaded by the driver output

And this may be the main routing constraint: to reduce wiring area, or wirelength

Although we have focused our attention to a single net until now…

… the routing problem lye over several other nets whose share the same routing area.

There are several other cells …

… with their respective pins …

… and they all should be properly connected.

Routing result by Parrot Tool Set. Screenshot from Yacif Viewer

The full layout for this example goes like this

Routing result example from Cadence Silicon EnsembleTM

Cells Internal layout is not available, only black boxes hiding the intelectual propriety of AMS STD Cell Designers

Highlighted the Filler-Cells (spaces) used for making feasible the routing step (subject for the 2nd part of this tutorial)

Please feedback-me: gbvsantos@inf.ufrgs.br

Interconnect Routing in VLSI

Interconnect Routing in VLSI

Presentation Transcript

Approximation Algorithms for VLSI Routing

VLSI

Parallel Algorithms for VLSI Routing

ECE 124a/256c VLSI RC(L) Interconnect Models

MinBD : Minimally-Buffered Deflection Routing for Energy-Efficient Interconnect

Introduction to VLSI Interconnect Design

Ant Colony Optimization for Cell Routing in VLSI Chips

IP interconnect

Interconnect Implications of Growth-Based Structural Models for VLSI Circuits*

IP Interconnect

Interconnect Optimizations

interconnect

Interconnect Centric VLSI Design Automation

EE4271 VLSI Design Interconnect Optimizations Buffer Insertion

Interconnect Networks

Interconnect Basics

MSAN Interconnect

Interconnect Length Estimation in VLSI Designs: A Retrospective

VLSI Online training |Online VLSI Course in Bangalore - VLSI GURU

ECE 124a/256c VLSI RC(L) Interconnect Models

Interconnect

Introduction to CMOS VLSI Design Interconnect: wire