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Final presentation

FPGA Based SAT Solver. Saleem Sabbagh & Najeeb Darawshy Supervisors: Mony Orbach, Technion & Ilia Averbouch, IBM. Final presentation. Started at: Winter 2012 Duration: Semester. outline. What is SAT Reminder - description and goals Flow diagram Circuit diagram

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Final presentation

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  1. FPGA Based SAT Solver Saleem Sabbagh & Najeeb Darawshy Supervisors: Mony Orbach, Technion & Ilia Averbouch, IBM Final presentation Started at: Winter 2012 Duration: Semester

  2. outline • What is SAT • Reminder - description and goals • Flow diagram • Circuit diagram • Example simulation results • Live Presentation • Runtimes • Compilation times • Notes & Conclusions • What’s Next

  3. What is sat • Boolean Satisfiability Problem • Given a Boolean propositional formula, does there exist assignment of values such that the formula becomes true? • e.g., given the formula f=(x1 ˅ x3˅ -x4) ˄ (x4) ˄ (x2 ˅ -x3) are there values of x1,x2,x3,x4 that produce f=‘1’

  4. Reminder – description and goals • Description: • Hardware based SAT Solver • Goals: • Implementing SAT instances into FPGA • Measuring build and run times for benchmark examples • Enabling further development of fast hardware based SAT Solver

  5. Flow diagram Programmable File Circuit Description as VHDL CNF Instances Synthesis Conversion Device Programmer FPGA Running SAT Solver PC DE2 Analysis and Timing Report

  6. circuit diagram F clk en sOUT timeOUT

  7. circuit diagram - LFSR • LFSR Random Generator (Generic width up to 168 bits)

  8. circuit diagram - Smartshift • A right shift register with Parallel Load, Shift Enable, Parallel and Serial output • While SAT still unsatisfiable F=0, NOT(F)=1 therefor: LOAD=1  D is loaded into register; SE=0  Shift not enabled. • When found satisfying input F=1, NOT(F)=0 therefor: LOAD=0  Stop Loading Parallel input; SE=1  Start shifting; MSB  Satisfying input.

  9. Example simulation results • For SAT instance of 20 variables and 91 clauses • Satisfying input: 00101011011101000000

  10. Runtime *Clock frequency is 50M [Hz]

  11. Compilation times *Clock frequency is 50M [Hz]

  12. Compilation times - Analysis • Compilation time is comprised of two main stages, Analysis & Synthesis and Place & Route. We found the problem to be associated directly to the peak interconnect usage during Place & Route stage.

  13. Notes • Tried several solutions for 1000-variables SAT with 4250 clauses in order to decrease compilation time: • Low Priority Optimization during Compliation – Did not help. • Better Altera board, Altera Stratix V – 85% cut in compilation time. • In order to better sample our variables spectrum, We have used two applications: • Java based Random SAT generator with 4.25:1 ratio (Clauses:Variables) which was used for compilation time analysis. • Cpp based satisfyable/unsatisfyable SAT generator used in official sat competitions which was used for runtimes analysis.

  14. Whats next • Two approaches • Improving runtimes by designing smart sat solver instead of inefficient LFSR random generator • Improving compilation times by: • Understanding Altera compilation algorithms to enable faster SAT-specific fpga ready files. • Smart use of memory on FPGA to implement SAT.

  15. Thank you! • Questions?

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