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Computer Organization

The Memory System. Computer Organization. Department of CSE, SSE Mukka. Chapter Objectives. Basic memory circuits Organization of the main memory Cache memory concept – Shortens the effective memory access time Virtual memory mechanism – Increases the apparent size of the main memory

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Computer Organization

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  1. The Memory System Computer Organization Department of CSE, SSE Mukka www.bookspar.com | Website for students | VTU NOTES

  2. Chapter Objectives • Basic memory circuits • Organization of the main memory • Cache memory concept – • Shortens the effective memory access time • Virtual memory mechanism – • Increases the apparent size of the main memory • Secondary storage • Magnetic disks • Optical disks • Magnetic tapes www.bookspar.com | Website for students | VTU NOTES

  3. Basic Memory Concepts • The maximum size of the Main Memory (MM) that can be used in any computer is determined by its addressing scheme. • For eg., • 16 – bit computer that generates 16-bit addresses is capable of addressing up to ? • 32 – bit computer with 32-bit address can address _____ memory locations • 40 – bit computer can address _______ memory locations www.bookspar.com | Website for students | VTU NOTES

  4. Word addressability and byte-addressability • If the smallest addressable unit of information is a memory word, the machine is called word-addressable. • If individual memory bytes are assigned distinct addresses, the computer is called byte-addressable. • Most of the commercial machines are byte-addressable. • For example in a byte-addressable 32-bit computer, each memory word contains 4 bytes. • A possible word-address assignment would be: • Word Address Byte Address • 0 0 1 2 3 • 4 4 5 6 7 • 8 8 9 10 11 www.bookspar.com | Website for students | VTU NOTES

  5. Basic Memory Concepts • Word length of a computer is the number of bits actually stored or retrieved in one memory access • For eg., a byte addressable 32-bit computer, whose instructions generate 32-bit addresses • High order 30 bit to determine which word in memory • Low order 2 bits to determine which byte in that word • Suppose we want to fetch only one byte from a word. • In case of Read operation, other bytes are discarded by processor • In case of Write operation, care should be taken not to overwrite other bytes www.bookspar.com | Website for students | VTU NOTES

  6. Basic Memory concepts • Data transfer between memory and the processor takes place through the use of 2 processor registers • MAR – Memory address register • MDR – Memory Data Register • If MAR is k bits long and MDR n bits long • Memory unit may contain up to 2k addressable locations • During a memory cycle, n bits of data are transferred between memory and the processor • No of address lines and data lines in processor? • There are additional control lines read/write, MFC, no of bytes to be transferred etc www.bookspar.com | Website for students | VTU NOTES

  7. Memory Processor k -bit address bus MAR n -bit data bus k Up to 2 addressable MDR locations Word length = n bits Control lines R / W ( , MFC, etc.) Figure 5.1.Connection of the memory to the processor. www.bookspar.com | Website for students | VTU NOTES

  8. How processor reads data from the memory ? • Loads the address of the required memory location into MAR • Sets R/W line to 1 • The memory responds by placing the requested data on data lines • Confirms this action by asserting MFC signal • Upon receipt of MFC signal, processor loads the data on the data lines in to the MDR register www.bookspar.com | Website for students | VTU NOTES

  9. How processor Writes Data into memory? • Loads the address of the location into MAR • Loads the data into MDR • Indicates Write operation by setting R/W line to 0 www.bookspar.com | Website for students | VTU NOTES

  10. Some concepts • Memory Access Times: - • It is a useful measure of the speed of the memory unit. It is the time that elapses between the initiation of an operation and the completion of that operation (for example, the time between READ and MFC). • Memory Cycle Time :- • It is an important measure of the memory system. It is the minimum time delay required between the initiations of two successive memory operations (for example, the time between two successive READ operations). The cycle time is usually slightly longer than the access time. www.bookspar.com | Website for students | VTU NOTES

  11. Random Access Memory (RAM) • A memory unit is called a Random Access Memory if • any location can be accessed for a READ or WRITE operation in some fixed amount of time that is independent of the location’s address. • Main memory units are of this type. • This distinguishes them from serial or partly serial access storage devices such as magnetic tapes and disks which are used as the secondary storage device. www.bookspar.com | Website for students | VTU NOTES

  12. Cache Memory • The CPU processes instructions and data faster than they can be fetched from compatibly priced main memory unit. • Memory cycle time becomes the bottleneck in the system. • One way to reduce the memory access time is to use cache memory. • Its a small and fast memory that is inserted between the larger, slower main memory and the CPU. • Holds the currently active segments of a program and its data. • Because of the locality of address references, • CPU finds the relevant information mostly in the cache memory itself (cache hit) • infrequently needs access to the main memory (cache miss) • With suitable size of the cache memory, cache hit rates of over 90% are possible www.bookspar.com | Website for students | VTU NOTES

  13. Memory Interleaving • This technique divides the memory system into a number of memory modules • Arranges addressing so that successive words in the address space are placed in different modules. • When requests for memory access involve consecutive addresses, the access will be to different modules. • Since parallel access to these modules is possible, the average rate of fetching words from the Main Memory can be increased www.bookspar.com | Website for students | VTU NOTES

  14. Virtual Memory • In a virtual memory System, the addresses generated by the program may be different from the actual physical address • the address generated by the CPU is referred to as a virtual or logical address. • The required mapping between physical memory and logical address space is implemented by a special memory control unit, called the memory management unit. • The mapping function may be changed during program execution according to system requirements. • The logical (virtual) address space • can be as large as the addressing capability of the CPU • The physical address space • the actual physical memory can be much smaller. www.bookspar.com | Website for students | VTU NOTES

  15. Virtual memory • Only the active portion of the virtual address space is mapped onto the physical memory • the rest of the virtual address space is mapped onto the bulk storage device like magnetic disks( hard disks) • If the addressed information is in the Main Memory (MM), it is accessed and execution proceeds. • Otherwise, an exception is generated, in response to which • the memory management unit transfers a contiguous block of words containing the desired word from the bulk storage unit to the MM, • displacing some block that is currently inactive. www.bookspar.com | Website for students | VTU NOTES

  16. b b ¢ b b ¢ b b ¢ 7 7 1 1 0 0 • • • W 0 FF FF A • • • 0 W 1 A 1 Address Memory • • • • • • • • • • • • • • • • • • cells decoder A 2 A 3 • • • W 15 R / W Sense / Write Sense / Write Sense / Write circuit circuit circuit CS Data input /output lines: b b b 7 1 0 Figure 5.2.Organization of bit cells in a memory chip. www.bookspar.com | Website for students | VTU NOTES

  17. An example of memory organization • A memory chip consisting of 16 words of 8 bits each, which is usually referred to as a 16 x 8 organization. •   The data input and the data output of each Sense/Write circuit are connected to a single bi-directional data line in order to reduce the number of pins required. • One control line, the R/W (Read/Write) input is used a specify the required operation and • another control line, the CS (Chip Select) input is used to select a given chip in a multichip memory system. • This circuit requires 14 external connections, and allowing 2 pins for power supply and ground connections, can be manufactured in the form of a 16-pin chip. • It can store 16 x 8 = 128 bits. www.bookspar.com | Website for students | VTU NOTES

  18. 5-bit row address W 0 W 1 32 ´ 32 5-bit memory cell decoder array W 31 Sense / Write circuitry 10-bit address 32-to-1 R / W output multiplexer and CS input demultiplexer 5-bit column address Data input/output Figure 5.3. Organization of a 1K  1 memory chip. www.bookspar.com | Website for students | VTU NOTES

  19. 1K X 1 memory chip • The 10-bit address is divided into two groups of 5 bits each to form the row and column addresses for the cell array. • A row address selects a row of 32 cells, all of which are accessed in parallel. • One of these, selected by the column address, is connected to the external data lines by the input and output multiplexers. • This structure can store 1024 bits, can be implemented in a 16-pin chip. www.bookspar.com | Website for students | VTU NOTES

  20. Static memories • Memories that consist of circuits capable of retaining their state as long as power is applied – static memories • Static rams can be accessed very quickly – few nanosecs www.bookspar.com | Website for students | VTU NOTES

  21. Bit line b b ¢ Two inverters 2 transistors T1 and T2 T T 1 2 X Y When word line is at ground level transistors are turned off, and latch retains its state Word line Bit lines Figure 5.4. A static RAM cell. www.bookspar.com | Website for students | VTU NOTES

  22. Read and Write operation in SRAM • Read • Word line is activated – to close switches T1 and T2 • If cell is in state 1, the signal on bit line b is high and signal on bit line b’ is low • Opposite holds if cell is in state 0 • Sense/Write circuits at the end of the bit lines monitor the states of b and b’ and sets output • Write • State of cell is set by placing appropriate value on bit line badn b’ and then word line is activated • This forces the cell into corresponding state • Required signals on bit lines are generated by Sense/Write circuit www.bookspar.com | Website for students | VTU NOTES

  23. www.bookspar.com | Website for students | VTU NOTES

  24. Dynamic RAMs • Static RAMs are fast but come at a higher cost • Their cells require several transistors • Less expensive RAMs using less no of transistors, • But their cells cannot retain their state indefinitely • Called as Dynamic RAMs • Information stored in the form of charge on a capacitor • This charge can be maintained only for tens of milliseconds • Contents must be periodically refreshed www.bookspar.com | Website for students | VTU NOTES

  25. Dynamic RAM – needs to refreshed periodically to hold data Bit line Word line T C Figure 5.6.A single-transistor dynamic memory cell www.bookspar.com | Website for students | VTU NOTES

  26. A 16-Mbit DRAM chip, configured as 2M X 8 • The cells are organized as 4K X 4K array • The 4096 cells in each row are divided into 512 groups of 8 • A row can hence store 512 bytes of data • 12 Address bits are required to select a row • 9 bits needed to specify a group of 8 bits in the selected row www.bookspar.com | Website for students | VTU NOTES

  27. Timing is controlled asynchronously. Specialized memory controller circuit to provide the necessary control signals CAS and RAS, that govern the timing. Hence it is asynchronous DRAM R A S 4096X(512X8) Row Row address decoder cell array latch A ¤ A CS Sense / Write 20 - 9 8 - 0 circuits R / W Column Column address decoder latch C A S D D 7 0 Figure 5.7. Internal organization of a 2M ´ 8 dynamic memory chip. www.bookspar.com | Website for students | VTU NOTES

  28. Fast Page mode • All bits of a row are sensed but only 8 bits are placed • This byte is selected by column address bits • A simple modification can make it access other bytes of the same row without having to reselect the row • Add a latch to the output of the sense amplifier in each column • The application of a row address will load latches corresponding to all bits in a selected row • Need only different column addresses to place the different bytes on the data lines • Most useful arrangement is to transfer bytes in sequential order • Apply a consecutive sequence of column addresses under the control of successive CAS signals. • This scheme allows transferring a block of data at a much faster rate than can be achieved for transfers involving random addresses • This block transfer capability is called as fast page mode www.bookspar.com | Website for students | VTU NOTES

  29. SYNCHRONOUS DRAMs • Operation directly synchronized with a clock signal • Called as SDRAMs • The cell array is the same as in Asynchronous DRAMs. • The address and data connections are buffered by means of registers • Output of each sense amplifier is connected to a latch • A read operation causes the contents of all cells in the selected row to be loaded into these latches • If an access is made for refreshing purposes only, it wont change the contents of these latches • Data held in the latches that correspond to the selected column(s) are transferred into the data output register www.bookspar.com | Website for students | VTU NOTES

  30. Refresh counter Row Ro w address Cell array decoder latch Row/Column address Column Co lumn Read/Write address circuits & latches decoder counter Clock R A S Mode register Data input Data output C A S and register register timing control R / W C S Data Figure 5.8.Synchronous DRAM. www.bookspar.com | Website for students | VTU NOTES

  31. SYNCHRONOUS DRAMs • SDRAMs have several different modes of operation • Selected by writing control information into a mode register • Can specify burst operations of different lengths • In SDRAMs, it is not necessary to provide externally generated pulses on the CAS line to select successive columns • Necessary signals are provided using a column counter and clock signal • Hence new data can be placed on data lines at each clock cycle • All actions triggered by rising edge of the clock www.bookspar.com | Website for students | VTU NOTES

  32. Clock R / W R A S C A S Address Row Col Data D0 D1 D2 D3 Figure 5.9.Burst read of length 4 in an SDRAM. www.bookspar.com | Website for students | VTU NOTES

  33. Burst read of length 4 in an SDRAM. • Row address latched under control of RAS signal • Memory takes about 2-3 cycles to activate selected row • Column address is latched under control of CAS signal • After delay of 1 cycle, first set of data bits placed on data lines • SDRAM automatically increments column address to access the next 3 sets of bits in the selected row, placed on data lines in successive clock cycles • SDRAMs have built in refresh circuitry • Provides the addresses of rows that are selected for refreshing • Each row must be refreshed at least every 64ns www.bookspar.com | Website for students | VTU NOTES

  34. Latency and Bandwidth • The parameters that indicate the performance of the memory • Memory latency – amount of time it takes to transfer a word of data to or from memory • In block transfers, latency is used to denote the time it takes to transfer the first word of data • This is longer than the time needed to transfer each subsequent word of a block • In prev diagram, access cycle begins with assertion of RAS and first word is transferred 5 cycles later. • Hence latency is 5 clock cycles www.bookspar.com | Website for students | VTU NOTES

  35. Bandwidth • Bandwidth usually is the no of bits or bytes that can be transferred in one sec • Depends on • Speed of memory access • Transfer capability of the links – speed of the bus • No of bits that can be accessed in parallel • Bandwidth is product of the rate at which data are transferred ( and accessed) and width of the data bus www.bookspar.com | Website for students | VTU NOTES

  36. Double – Data – Rate SDRAM ( DDR SDRAMs) • The standard SDRAM performs all actions on the rising edge of the clock signal • DDR SDRAMs access the cell array in same way but transfers data on both the edges of the clock • The latency is the same as standard SDRAMs • But since they transfer data on both the edges of clock, bandwidth is essentially doubled for long burst transfers • To make this possible, the cell array is organized into 2 banks • Each bank can be accessed separately • Consecutive words of a given block are stored in different banks • Efficiently used in applications where block transfers are prevalent • Eg., main memory to and from processor caches www.bookspar.com | Website for students | VTU NOTES

  37. Questions for assignment • 1. Explain how processor reads and writes data fromadn to memory • 2. explain organization of 1K X 1 memory chip • 3. Explain a single SRAM cell with diagram. How read and write operations are carried out? • 4. Explain DRAM cell with diagram. How read and write operations are carried out? • 5. Explain 2M X 8 DRAM chip. How can you modify this for fast page mode • 6. Explain SDRAMs with help of a diagram • 7. Explain the terms latency and bandwidth • 8. Explain the burst length read of 4 in SDRAM with timing diagram • 9. Explain DDR SDRAMs www.bookspar.com | Website for students | VTU NOTES

  38. Structure of larger memories • Memory systems connected to form larger memories • There are 2 types of memory systems • Static memory systems • Dynamic memory systems www.bookspar.com | Website for students | VTU NOTES

  39. Static Memory systems • Following is the diagram for implementation of 2M X 32 memory using 16 512K X 8 static memory chips • There are 4 columns, each column containing 4 chips to implement one byte position • Only selected chips ( using chip select input ) place data on output lines • 21 address bits are needed to select a 32 bit word in this memory • high order 2 bits used to determine which of the 4 chip select signals should be activated • 19 bits used to access specific byte locations inside each chip of selected row • R/W inputs of each chip are tied together to form a single R/W signal • Dynamic memory systems are organized much in the same manner as static • Physical implementation more conveniently done in the form of memory modules www.bookspar.com | Website for students | VTU NOTES

  40. 21-bit addresses 19-bit internal chip address A 0 A 1 A 19 A 20 2-bit decoder 512 K X 8 memory chip D D D D 31-24 23-16 15-8 7-0 memory chip 512 K X 8 19-bit 8-bit data address input/output Chip select www.bookspar.com | Website for students | VTU NOTES Figure 5.10. Organization of a 2M  32 memory module using 512K  8 static memory chips.

  41. Memory System Considerations • The choice of a RAM for a given system depends on several factors • Cost • Speed • Power dissipation • Size of chip • Static RAMs are used when very fast operation is the primary requirement • Used mostly in cache memories • Dynamic RAMs are predominant choice for computer main memories • High densities achievable make larger memories economically feasible www.bookspar.com | Website for students | VTU NOTES

  42. Memory Controller • To reduce number of pins, dynamic memory chips use multiplexed address inputs • Address divided into 2 parts • High-order address bits, to select a row in a cell array, are provided first and latched into memory under control of RAS • Low-order address bits, to select a column, are provided on the same address pins and latched under CAS signal • Processor issues all bits of address at the same time • The required multiplexing of address bits are performed by a memory controller circuit, www.bookspar.com | Website for students | VTU NOTES

  43. Row/Column address Address R A S R / W C A S Memory controller Request R / W Processor Memory C S Clock Clock Data Figure 5.11. Use of a memory controller. www.bookspar.com | Website for students | VTU NOTES

  44. Memory controller functions • Interposed between processor and memory • Processor sends Request signal • Accepts complete address and R/W signal from the processor • The controller forwards the row and column portions of address to the memory • Generates the RAS and CAS signals • Also sends R/W and CS signals to the memory • Data lines are directly connected between the processor and the memory • When used with DRAM chips, the memory controller provides all the information needed to control the refreshing process • Contains a refresh counter – to refresh all rows within the time limit specified for a device www.bookspar.com | Website for students | VTU NOTES

  45. RAMBUS Memory • To increase the system bandwidth we need to increase system bus width or system bus speed • A wide bus is expensive and required lot of space on motherboard • Rambus – narrow bus but much faster • Key feature is fast signaling method used to transfer information between chips • Uses the concept of differential signaling • Instead of either 0 volts or Vsupply ( 5 Volts ), uses 0.3 volt differences from a reference voltage called as Vref www.bookspar.com | Website for students | VTU NOTES

  46. READ-ONLY Memories (ROMs) • Both SRAMs and DRAMs are volatile • Loses data if power is turned off • Many applications need to retain data even if power is off • E.g., a hard disk used to store information, including OS • When system is turned on , need to load OS from hard disk to memory • Need to execute a program that boots OS • That boot program, since is large, is stored on disk • Processor must execute some instructions that load boot program into memory • So we need a small amount of non volatile memory that holds instructions needed to load boot program into RAM • Special type of writing process to place info into non volatile memories • Called as ROM – Read Only Memory www.bookspar.com | Website for students | VTU NOTES

  47. Not connected to store a 1 Connected to store a 0 Bit line Word line T P Figure 5.12.A ROM cell. www.bookspar.com | Website for students | VTU NOTES

  48. ROM • Transistor is connected to ground at point P then 0 is stored • Else 1 is stored • Bit line connected to a power supply through a resistor • To read, word line is activated • If voltage drops down – then 0 • If voltage remains same – then 1 www.bookspar.com | Website for students | VTU NOTES

  49. PROM • Allows data to be loaded by the user • Achieved by inserting a fuse at point P in the prev figure • Before it is programmed, memory contains all 0s • The user can insert 1at required locations using high-current pulses • Process is irreversible www.bookspar.com | Website for students | VTU NOTES

  50. EPROM • Allows the stored data to be erased and new data to be loaded • Erasable, reprogrammable ROM – called as EPROM • Can be used when memory is being developed • So that it can accommodate changes • Cell structure is similar to ROM • The connection to ground is always made at point P • A special transistor is used – ability to function either as a normal transistor or as a disabled transistor which is always turned off • Can be programmed to behave as permanently open switch • Can erase by exposing the chip to UV light which dissipate the charges trapped in transistor memory cells www.bookspar.com | Website for students | VTU NOTES

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