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GEM 型放射線イメージング装置用フロントエンド LSI の開発

GEM 型放射線イメージング装置用フロントエンド LSI の開発. 2007 年 12 月 15 日 4 th MPGD 研究会＠大阪市大 房安貴弘 1 ＊ 、佐野哲 2 、田中義人 1 、浜垣秀樹 2 1 長崎総合科学大学 2 東京大学原子核科学研究センター. Motivation. GEM を用いた X 線イメージングや中性子線イメージングのため、専用のフロントエンド LSI を開発。. X 線の場合。 考古学のフィールドワークや医療用など. 中性子線の場合。 エンジン中の液体の動的観察など. Pixel Readout Method.

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GEM 型放射線イメージング装置用フロントエンド LSI の開発

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  1. GEM型放射線イメージング装置用フロントエンドLSIの開発GEM型放射線イメージング装置用フロントエンドLSIの開発 2007年12月15日 4th MPGD研究会＠大阪市大 房安貴弘1＊、佐野哲2、田中義人1、浜垣秀樹2 1長崎総合科学大学 2東京大学原子核科学研究センター

  2. Motivation • GEMを用いたX線イメージングや中性子線イメージングのため、専用のフロントエンドLSIを開発。 X線の場合。 考古学のフィールドワークや医療用など 中性子線の場合。 エンジン中の液体の動的観察など

  3. Pixel Readout Method ① Pixels on LSI ② Multiple LSI’s Max Size = 2cm x 2cm 2 x 2 LSI’s are maximumbecause of bonding pads → Max size = 4cm x 4cm NIM A535 (2004) 477 ④ Use TFT process for LCD ③ PCB Bd Difficulty inwiring. → Min. pixel size = about 1mm2 Difficulty in availability

  4. Incident signalon GEM sheet Trigger Clock Analog Out ・・・・・・・・・・・ CH1 2 3 4 5 Readout Circuit For Still X-ray Imaging • Still Imaging. • We want to obtain information per particle.

  5. Readout Circuit For Motion Imaging by Neutron Imaging rate = about 100rps x 10frames = 1０００fps → Need fast readout Frame Signal • 1ms積分の後、読出し、放電。 • 放電直後のベースライン電位も測定。

  6. Prototype Strategy • w/o peak-hold circuit and shaper because of integration mode for neutron imaging. • w/o output buffer. • Trigger is given by user. • Use TSMC 0.25mm1P5M n-well process.VDD=2.5V.

  7. Shift Register Compensating dummy switch Discharge switch from the previous channel to thenext channel SwitchControl 1pF Pixel Charge Input 1pF MUX Folded-CascodeOPamp Over-VoltageProtectionW/L=8mm/4mm Test Pulse Input Schematic of Channel

  8. Schematic of OP amp OP amp feature obtained by simulation Standard Folded-Cascode OP amp

  9. Layout Design Process: TSMC 0.25mm 1P5M n-well Chip size: 5mm×2.5mm The design has been submitted for fabrication. The chip has been obtained in Nov/2007. 1ch circuit 5mm 230um MUX OPamp Shift Register switch Capacitors 2.5mm

  10. Layout Simulation • Parasitic RC’s are extracted. Analog Output of the Chip (i.e. MUX out) Rise time = 50ns. Setting time = 160ns (0.1%). Droop of the Capacitor 7mV droop during a frame period, of which 4mV is due to the discharge switch.

  11. Layout Simulation • Total power dissipation of the chip : 75mW • Crosstalk between neighboring channels : 0.01% • Clock migration to the analog out : 10mVpp

  12. PCB Design

  13. PCB Circuits • ＬＳＩからの出力領域　　　0.75-1.75V (Vref=0.75V) • ADC(AD7825)のconversion 領域　　　0-2.5V 0.75-1.75V 0.1-2.4V ADC : 8bit 3.3p 1k 1.3k 1.5V 1k 1.5k

  14. PCB Fabricated with ASIC

  15. Summary and Future • Frontend ASIC for GEM imaging was fabricated using TSMC 0.25mm process. • Layout simulation has been done. • System test using GEM chamber will be performed @ CNS. • Single chip test will be performed @ Nagasaki. • Integrate with pipelined ADC?

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