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Athens University Paris Sphicas Vassilis Karageorgos (Diploma) NCSR Demokritos Theo Geralis

Global Trigger Processor Emulator. Dr. Katerina Zachariadou. Athens University Paris Sphicas Vassilis Karageorgos (Diploma) NCSR Demokritos Theo Geralis Christos Markou Isidoros Michailakis (Electronics Engineer) Katerina Zachariadou. Global Trigger Processor.

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Athens University Paris Sphicas Vassilis Karageorgos (Diploma) NCSR Demokritos Theo Geralis

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  1. Global Trigger Processor Emulator Dr. Katerina Zachariadou Athens UniversityParis Sphicas Vassilis Karageorgos (Diploma) NCSR DemokritosTheo Geralis Christos Markou Isidoros Michailakis (Electronics Engineer) Katerina Zachariadou

  2. Global Trigger Processor Timing, Trigger & Control optical network RTP TPG FES LV1 TTC FED BackPressure GTP TTS FRL GTP BackPressure RCN RU LV1A EVM BDN BCN BU

  3. TTC GTP TTS EVM Global Trigger Emulator Tasks: • Generate Level-1 triggers (according to trigger rules). • Sent triggers to TimingTriggerControl system • Generate Event Number, BX counts and Trigger record data to be sent to the Event Manager (via S- Link64) • Receive Trigger Throttling System levels (Ready, Busy, Error)

  4. GTP-EVM-TTS simulation Vassilis Karageorgos University of Athens Diploma work Global Trigger Processor Running on PC#1 Intercommunication between programs via TCP/IP sockets Trigger Throttling System Running on PC#3 Event Manager Running on PC#2

  5. TTC-ex TTC-vi VME G3 G3 PCIbus PCIbus GTP emulation Hardware components (final) FEDs TTS PC#3: Windows 2000 Quartus + DK1: FPGA code PCI-MXI2-VME LV1Acc PC#1:Linux OS Control VME Control G3 S-LINK64 PC#2: Linux OS EVM emulation

  6. B E D A C F S-LINK64 GENERIC-III , S-LIN64 A. FPGA (APEX –Altera 200K usable logic gates) B. 32 MB SDRAM (133Mhz) C. 1 MB Flash D. S_Link64 connectors (data transmission) E. User connectors F. PCI interface for 32b/64b @33/66MHz

  7. S-LIN64 Data link to connect front-end to readout at any stage in a dataflow environment Data movement,error detection, return channel for flow control CMC receiver card: Converts LVDS signals to S-LINK64 signals On-board FIFO(32Kbytes) buffers incoming data CMC transmitter card: Converts S-LINK64 signals to LVDS format

  8. TTC-ex TTC-vi VME G3 G3 PCIbus PCIbus GTP emulation Hardware components (Actual) FEDs Dig. Oscilloscope HP54615B For hardware tests TTS PC#3: Windows 2000 Quartus + DK1: FPGA code PCI-MXI2-VME LV1Acc PC#1: Linux OS Labview 6.1/RUlib Control PCI bus Control G3 S-LINK64 LV1Acc PC#2: Linux OS EVM emulation

  9. OS: WindowsXX PCI bus PC Parallel port with a byte-blaster GTP emulator schematic Altera logic layout VHDL, AHDL DK1.1 Celoxica software In Handel-C Quartus 2.2-Altera software PCI control GTP emulation SDRAM control SLINK-64 control OS: Linux

  10. PCI control • PCI Controller: • PCI communication (Dominique Gigi-CERN) • Registers for Control, Status, Error, Reset operations (Isidoros Michailakis)

  11. GTP- transmitter S-LINK64 CONTROL GTP -transmitter Command PCI control MEM_FULL Local FIFO GTP S-LINK64 (Back_Pressure) WRITE_MEM DATA[63..0] S-LINK64 MEM_FULL DATA[63..0]

  12. EVM-receiver S-LINK64 CONTROL Command PCI control Local FIFO S-LINK64 DATA[63..0] DATA[63..0]

  13. S-LINK64 control S-LINK64 Controller (by Isidoros) Read local fifo Transfer data transmitter PCI BackPressure

  14. GTP- part Lemo Output LV1A bxn BX_gen BX Bx_Rndm evn Write_evm S-LINK64 BackPressure FIFO_full (Backpressure) Local FIFO DATA[63..0] GTP_to_EVM_data (evn[31:12]+bxn[11:0])

  15. BX generator module DK1 module that generates the LHC proton beam structure (40.8MHz) 3564 bunches = {[(72b +8e)x3+30e]x2+[(72b+8e)x4+31e]}x3 + {[(72b+8e)x3+30e]x3+81e} Clock = 80 MHz (for tests used the PCI clock @33MHz ) • BX is created as in LHC • LV1Acc occurs only on full bunches Simulator output:

  16. BX_Rndm module Lemo Output LV1A bxn BX_gen BX Bx_Rndm evn Write_evm S-LINK64 BackPressure FIFO_full (Backpressure) Local FIFO DATA[63..0] GTP_to_EVM_data (evn[31:12]+bxn[11:0])

  17. BX_rndm module BX_rndm module tasks: • Random number generator (22 bits long  Period = 4x106 events) • At non empty BXs generates LV1Accept signals randomly at a frequency of 100KHz (or at any frequency [4Hz, 100KHz]) • Associates a BX Number [0,3563] and an Event Number

  18. CLK BX_rndm module BXN LV1-A rate LV1A BX DK1 Handel-C code  Edif file  Symbol for BX_rndm in Quartus EVN

  19. LV1A on the scope For this test LV1A @ 50KHz

  20. Write_Evm module Lemo Output LV1A bxn BX_gen BX Bx_Rndm evn Write_Evm S-LINK64 BackPressure FIFO_full (Backpressure) Local FIFO DATA[63..0] GTP_to_EVM_data (evn[31:12]+bxn[11:0])

  21. Write_Evm module BX number 1. Prepares data to be sent to the local FIFO 2. Checks the FIFO full flag (BackPressure) 3. Writes data in FIFO if not full. If the local FIFO is full the data are lost. event number DATA[63..0] FIFO full WEN

  22. Write_Evm module timing

  23. Local FIFO Lemo Output LV1A bxn BX_gen BX Bx_Rndm evn Write_evm S-LINK64 BackPressure FIFO_full (Backpressure) Local FIFO DATA[63..0] GTP_to_EVM_data (evn[31:12]+bxn[11:0])

  24. Local FIFO LOCAL FIFO (by Isidoros) FIFO : 1024 x 64 bits words, rw MUX for accessing the Control, Status etc registers

  25. GTP EVM via SLINK-64 tests GTP vi running on PC#1: Generate Level1 Accept triggers at user defined frequency Send data to the Event Manager Receiver vi running on PC#2: Get data

  26. Dig. Oscill Quartus + DK1: FPGA code Control G3+VME LV1A SLINK-64 GTP EVM Summary TTC TTS GTP EVM • GTP emulator conceptual design • LHC beam structure, LV1A signal , EVN, BXN • SLINK-64 control • GTP EVM via SLINK-64

  27. TTC FED LV1A TTS GTP EVM BackPressure Future Plans Further tests of the design+integration tests of all components in a complete GTP emulator : • BackPressure signals from TTS & EVM • Generate Level-1 triggers according to trigger rules • Implement Trigger Summary Block • FEDkit emulator as receiver TTS signals Ready Busy inhibit Synchr. failure inhibit + synchr command via TTC to FED’s (reset counters) Overflow reduction of trigger rate set of Trigger Rules : “No more than N Level-1 Triggers in a given time interval”.

  28. Dig. Oscill Quartus + DK1: FPGA code Control G3+VME LV1A SLINK-64 GTP EVM Conclusions • GTP emulator conceptual design • LHC beam structure, LV1A signal , EVN, BXN • SLINK-64 control • GTP EVM via SLINK-64

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