CSCE 932, Spring 2007

1. CSCE 932, Spring 2007 Yield Analysis and Product Quality

2. Yield Analysis & Product Quality • Yield, defect level, and manufacturing cost • Clustered defects and yield model • Test data analysis • Example: SEMATECH chip • Summary

3. ALL CHIPS Test (Tester Yield) FAIL PASS Bad Good Good Good/Bad? Bad Good/Bad? Bad Good Tested As Bad Bad Tested As Good Good (Yield) (Ybg) (Reject Rate or DPM) (Yield Loss) (Overkill) Test Performance These two items determine the tester performance

4. Reject Rate (DPM) Basics • Reject Rate or Defectives per million (DPM) is a measure of product quality • Zero DPM can be achieved by: • Perfect yield (100% yield => no bad parts) • Perfect test (100% coverage => all bad parts eliminated in testing, all good parts passed) • Neither fabrication nor testing process is perfect hence non-zero DPM is a fact of life. • DPM minimization is an important goal of quality-conscious companies. • For commercial VLSI chips a DL greater than 500 dpm is considered unacceptable.

5. Ways to Estimate DPM • Field-Return Data • Get customers to return all defective parts, then analyze and sort them correctly to estimate DPM • DPM Modeling and Validation • Analytical approach using yield and test parameters in the model to predict yield. Steps: • Develop a model • Calibrate it (Determine parameter values) • Estimate the DPM • Verify against actual measurements • Recalibrate in time and for new designs or processes

6. VLSI Chip Yield and Cost • Manufacturing Defect: Chip area with electrically malfunctioning circuitry caused by errors in the fabrication process. • Good Chip: One without a manufacturing defect. • Yield (Y): Fraction (or percentage) of good chips produced in a manufacturing process is called the yield. • Chip Cost:

7. Clustered VLSI Defects Good chips Faulty chips Defects Wafer Clustered defects (VLSI) Wafer yield = 17/22 = 0.77 Unclustered defects Wafer yield = 12/22 = 0.55

8. Yield Modeling • Statistical model, based on distribution of defects on a chip: • p(x) = Prob(number of defects on a chip = x) • Yield = p(0) • Empirical evidence shows that defects are not uniformly randomly distributed but are clustered. • A form of negative binomial pdf is found to track well with observed data.

9. Binomial and Negative Binomial pdf • Bernoulli trials: A biased coin with success probability = p is tossed repeatedly. • Binomial: If the coin is tossed n times what is the probability of x successes? • Negative Binomial: What is the probability of x failures occurring before the r-th success?

10. Mathematical Definitions • Binomial: • Negative Binomial*: * “Negative” comes from the fact the the distribution can also be written as

11. Generalized Negative Binomial Distribution • When r is a non-integer, the above interpretation breaks down but the form is useful in modeling count data:

12. For modeling the defect distribution we make the following substitutions in the above eqn: where, d = Defect density = Average number of defects per unit of chip area A = Chip area a = Clustering parameter

13. Defect Distribution Equation p(x) = Prob(number of defects on chip =x)

14. Yield Equation Y = Prob ( zero defect on a chip ) = p (0) Y = ( 1 + Ad / a ) - a Example: Ad = 1.0, a = 0.5, Y = 0.58 , Y = e - Ad Unclustered defects: a = Example: Ad = 1.0, a = , Y = 0.37 too pessimistic !

15. Determination of DL from Test Data (Basic Idea) • Combine tester data: • #chips passing vs. test-pattern number with the fault coverage data: • cum. fault coverage vs. test-pattern number to derive the data: • #chips passing vs. fault coverage • Extend the defect model to a fault model (yield of chips vs. fault coverage) and determine its parameters by curve fitting.

16. Modified Yield Equation • Three parameters: • Fault density, f = average number of stuck-at faults per unit chip area • Fault clustering parameter, b • Stuck-at fault coverage, T • The modified yield equation: Y (T ) = (1 + TAf / b) - b Assuming that tests with 100% fault coverage (T =1.0) remove all faulty chips, Y = Y (1) = (1 + Af / b) - b

17. Defect Level Y (T ) - Y (1) DL (T ) = -------------------- Y (T ) ( b + TAf ) b = 1 - -------------------- ( b + Af ) b Where T is the fault coverage of tests, Af is the average number of faults on the chip of area A, b is the fault clustering parameter. Afand b are determined by test data analysis.

18. Example: SEMATECH Chip • Bus interface controller ASIC fabricated and tested at IBM, Burlington, Vermont • 116,000 equivalent (2-input NAND) gates • 304-pin package, 249 I/O • Clock: 40MHz, some parts 50MHz • 0.45m CMOS, 3.3V, 9.4mm x 8.8mm area • Full scan, 99.79% fault coverage • Advantest 3381 ATE, 18,466 chips tested at 2.5MHz test clock • Data obtained courtesy of Phil Nigh (IBM)

19. Test Coverage from Fault Simulator Stuck-at fault coverage Vector number

20. Measured Chip Fallout Measured chip fallout Vector number

21. Model Fitting Chip fallout vs. fault coverage Y (1) = 0.7623 Chip fallout and computed 1-Y (T ) Measured chip fallout Y (T ) for Af = 2.1 and b = 0.083 Stuck-at fault coverage, T

22. Computed DL 237,700 ppm (Y = 76.23%) Defect level in ppm Stuck-at fault coverage (%)

23. Summary • VLSI yield depends on two process parameters, defect density (d ) and clustering parameter (a) • Yield drops as chip area increases; low yield means high cost • Fault coverage measures the test quality • Defect level (DL) or reject ratio is a measure of chip quality • DL can be determined by an analysis of test data • For high quality: DL < 500 ppm, fault coverage ~ 99%