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Tartu Ülikool , 2 3 . mai 200 3

Tartu Ülikool , 2 3 . mai 200 3. Otsustusdiagrammid e kasutamisest digitaalsüsteemide diagnostika s Raimund Ubar TTÜ, Arvutitehnika instituut. Otsustusdiagrammid e digitaalsüsteemide diagnostika. Ülevaade: Digitaalsüsteemide diagnostika põhiülesanded Otsustusdiagrammid: BDD ja SSBDD

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Tartu Ülikool , 2 3 . mai 200 3

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  1. Tartu Ülikool, 23. mai 2003 Otsustusdiagrammide kasutamisest digitaalsüsteemide diagnostikasRaimund UbarTTÜ, Arvutitehnika instituut

  2. Otsustusdiagrammide digitaalsüsteemide diagnostika Ülevaade: • Digitaalsüsteemide diagnostika põhiülesanded • Otsustusdiagrammid: BDD ja SSBDD • Boole’i operatsioonid (SS)BDD-dega • SSBDD-de omadused • Kõrgtaseme otsustusdiagrammid (DD-d) • register-edastuste tase • käsusüsteemi tase • Mitmedimensionaalsed otsustusdiagrammid

  3. Introduction – Test Tools Test experiment Test result System Fault simulation Fault diagnosis System model Fault table Test Go/No go Located defect Test generation Test tools

  4. Introduction – Test Tasks Fault Diagnosis and Test Generation as direct and reverse mathematical tasks: dy = F(x1, ... , xn) F(x1 dx1 , ... , xndxn) dy = F(X, dX) • Direct task: • Test generation: dX,dy = 1 given, X = ? • Reverse task: • Fault diagnosis: X,dy given, dX = ? • Fault simulation: X,dy = 1 given, dxk = ? Fault Simulationis aspecial case of fault diagnosis

  5. Binary Decision Diagrams • 1959 - Lee C.Y. - Description of BF by graph-like structures • 1967 - Ehrenfeucht A., Orlowska E - Fast evaluation of BE • 1971 - Schneider B.N. - Representing BF by graphs (Abstract) > AG • 1974 -Dipl. Thesis, TTU (Vaher/Ubar) - Fast evaluation of BE • 1975 -Breitbart Y, Reiter A. - Fast evaluation of BE (Compiler design) • 1976 - Ubar R. - Test generation > AG • 1976 - Kuzmin V.A. - Complexity evaluation of BF by BP • 1977 - Kuznetsov O.P. - Realization of BF by programmes • 1977 - Akers S.B. -Test generation, introduced the name BDD • 1981 - Thayse A. - BDDs in other fields: CAD, program optimization, AI • 1986 - Bryant R.E. - manipulation of BDDs • 1990 - Bryant R.A. - the first BDD package

  6. Binary Decision Diagrams y 1 Functional BDD x1 1 0 x2 x3 Simulation: x4 x5 0 1 1 0 1 0 0 Boolean derivative: x6 x7 0

  7. Binary Decision Diagrams BDDs for flip-flops S D Flip-Flop J JK Flip-Flop q c D q D C S C K q’ c q’ R K R RS Flip-Flop q’ J q c S S R C q’ q’ U R R U - unknown value

  8. Elementary BDDs Elementary BDDs: AND x1 x1 x2 x1 x2 x3 y & x2 y x3 + Adder x3 x1 OR x2 x1 y 1 y x1 x2 x3 x3 x2 x2 x3 x3 NOR x1 x2 y x1 x2 x3 1 x3

  9. Building a SSBDD for a Circuit Structurally Synthesized BDDs: DD-library: y a b Given circuit: x1 x1 x22 a a b x21 & x2 y x21 x3 1 x22 & SSBDD x3 Superposition of DDs b y x22 x22 a y x1 Compare to x3 x3 Superposition of Boolean functions: x21 b a

  10. Boolean Operations with BDDs x1 y x22 x1 AND-operation: a x21 & x2 y = e  g x3 x21 1 x22 e & x3 b y x4 x52 x4 c x6 x51 x51 & x5 g 1 x52 OR-operation: & x4 x1 y x52 x6 x22 d y = e  g x6 x51 x3 x21

  11. Boolean Operations with BDDs Boolean function: Inverted function: y = x1x2 x3 y = x1x2 x3 = (x1 x2) x3 y y x1 x2 x1 x3 x3 x2 Dual function: Inverted dual function: y * = x1x2 x3 y*= (x1 x2) x3 y * y* x1 x2 x1 x3 x3 x2

  12. BDD and DNF/KNF Boolean function:y= x1x2 x3 (x4  x5x6) Each 1-path represents a term in the DNF, each 0-path represents a term in the KNF y x1 x2 y x1 x2 x3 x4 x3 x4 x5 x6 x5 x6 1 0 x1x4x5 = 1 x3x5x6 = 1

  13. Transformation Rules for SSBDDs SSBDD BOOLEAN ALGEBRA Exchange of nodes: Commutative law: y y y = x1 x2= x2 x1 x1 x2 = x2 x1 Node passing: Idempotent law: y y x1 x1 y = x1 x1 x2 = = x1 x2 = x1 x1 x2 x2

  14. Transformation Rules for SSBDDs SSBDD BOOLEAN ALGEBRA Node passing: Absorption law: y y x1 x1 y = x1 x1x2 = x1 = x1 x2 x1 x2 Distributive law: y y x1 x1 x2 x2 y = x1x2  x1x3= = x1(x2  x3) = x1 x1 x3 x3

  15. Transformation Rules for SSBDDs SSBDD BOOLEAN ALGEBRA Superposition: y y y z x1 x1 Assotiative law: x3 z x2 = = y = x1 (x2  x3) = = (x1  x2)  x3 z z x1 x2 x3 x2 x3

  16. Transformation Rules for BDDs Change-over switching of nodes: Removing subgraphs: y y x1 x2 x1 x3 = y x1 x2 x3 x2 = x1 x3 Joint use of subgraphs: y y y x1 x2 x1 x3 x1 x3 = = x3 x2 x2 x2

  17. Macro 1 y & d 2 73 6 & 71 a 1 & e 3 72 7 b 4 5 1 y & 5 73 c 6 71 72 2 0 & & & Representing by SSBDD a Circuit Structurally synthesized BDD for a subcircuit (macro) To each node of the SSBDD a signal path in the circuit corresponds y = cyey = cyey = x6,e,yx73,e,y deybey y = x6x73  ( x1  x2 x71) ( x5 x72)

  18. SSBDDs vs. BDDs Advantages of SSBDDs compared to the BDDs: • Complexity explosion is avoided • The number of nodes is linear with the circuit size (determined by the number of paths in macros) • Test-specific structural features can be represented • Each node represent a signal path in the circuit • Faults of the circuit are directly represented in SSBDDs • Circuit’s dynamic (hazards, risk, delays) can be investigated with SSBDDs • Processing speed can be increased due to special properties of SSBDDs • Test generation (search space can be reduced) • Fault simulation (the speed of fault analysis can be increased) • Fault diagnosis (minimization of experiments easily controlled) Disadvantage:SSBDDs cannot be minimized

  19. N A B SSBDDs vs. BDDs Increasing the Speed of Test Generation with SSBDDs Task: Activate a path to 1 Result: Tracing is forced in nodes 1,9,10  Output 0 Another trials possible from 2,3,4  Not needed Property of SSBDD: 1 9 11 4 1 5 2 3 Breake search here 7 8 6 Theorem: In SSBDD there exists always a path between the two successors A and B of N, either from A to B or from B to A 10 0

  20. Macro 1 & d 2 & 71 a & e 3 72 7 b 4 y & 5 73 c 6 & & & SSBDDs vs. BDDs Increasing the Speed of Fault Simulation with SSBDDs Theorem: If a path in SSBDD is activated by a test pattern to 0 (or 1), then no faults can be detected by this pattern at nodes left in the oposite direction 1 (or 0) Example: y 73 6 1 5 1 71 72 2 The activated path is shown in bold The output value is 1 No need of fault simulation in nodes 6 and 1

  21. SSBDDs vs. BDDs Increasing the Speed of Fault Location with SSBDDs Circuit under guided probing: Error signal traced Error detected Where to continue pinpointing? ... C Theorem: If a path in SSBDD is activated to 0 (or 1), and an error is observed on the output, then no faults at nodes left in oposite direction 1 (or 0) can be the causes of the error SSBDD for the component C: 1 8 6 4 1 7 5 2 3 The activated path is shown in bold The output value is 0 Faults can be detected only in nodes 1,6,7

  22. SSBDDs vs. Gate-Level Models Advantages of SSBDDs compared to the Gate-Level Models: • Complexity reduction • Faults domain: each node represent all the faults of the corresponding signal path (fault collapsing) • Time domain: each node represent the delay of the corresponding signal path • Hierarchical approaches are easy • SSBDD for a subcircuit can be represented as a macro • No special manipulation procedures for different macros are needed • No model libraries for different tools are needed

  23. Extentions of BDDs • 1980 - Multi-Terminal DDs for uncertainty in sequential circuits (1993) • Automatika I Telemehanika, No5, 1980 • 1981 - Word-Level DDs for Data-Paths • Nachrichtentechnik-Elektronik 31 (1981, H.1) • 1983 - DDs with multi-output internal nodes • Proceedings of TTU No. 550 • 1983 - Vector DDs for output behaviour of microprocessors • Fault-Tolerant Computing Symposium, Milano Recent papers on high-level DDs: • R.Ubar. Test Synthesis with Alternative Graphs. J.of IEEE Design and Test of Computers. Spring, 1996, pp.48-59 • R.Ubar. Combining Functional and Structural Approaches in Test Generation for Digital Systems. J. of Microelectronics and Reliability, Elsevier Science Ltd. Vol. 38, pp.317-329, 1998 • J.Raik, R.Ubar. Fast Test Pattern Generation for Sequential Circuits Using Decision Diagram Representations. J. of Electronic Testing. Kluwer Acad. Publ.Vol. 16, No. 3, pp. 213-226, 2000. • R.Ubar, A.Morawiec, J.Raik. Back-Tracing and Event-Driven Techniques in High-Level Simulation with DDs. IEEE ISCAS’2000 Conf., Geneva, May 28-31, 2000, Vol. 1, pp. 208-211.

  24. New features: representing vectors multi-output internal nodes multi-terminal BDDs 3 1 4 1 5 1 q’ q.y 2.1 x1 Res 6 0 x1 1 3.0 7 2 8 1 x2 4.1 2 1.0 0 9 3 x2 5.0 4 10 6.1 11 1 5 x1 12 0 6 x1 1.0 * 13 *.0 Generalization of MTBDDs for FSMs State Transition Diagram: Res 1/0 x1 3/0 2/1 x2 4/1 5/0 x1 6/1

  25. High-Level Decision Diagrams R Superposition of High-Level DDs: A single DD for a subcircuit 2 0 y # 0 4 1 R 2 M1 0 0 2 y y R + R 3 1 1 2 R2 1 IN + R 2 1 IN 2 R 1 3 0 y R * R 2 R2 +M3 1 2 1 IN* R 2 M2 Instead of simulating all the components in the circuit, only a single path in the DD should be traced

  26. Faults and High-Level Decision Diagrams K: (If T,C) RD F(RS1,RS2,…RSm),  N RTL-statement: • Terminal nodes • RTL-statement faults: • data storage, • data transfer, • data manipulation faults • Nonterminal nodes • RTL-statement faults: • label, • timing condition, • logical condition, register decoding, • operation decoding, • control faults

  27. High-Level Decision Diagrams Register-Level Data Path:

  28. High-Level Decision Diagrams Representing transparency functions in Decision Diagrams

  29. DD Synthesis from Behavioral Descriptions Procedural description of a microprocessor BEGIN Memory state: M Processor state: PC, AC, AX Internal state: TMP Instruction format: IR = OP. A. F0. F1. F2. Execution process: EXEC: BEGIN DECODE OP  ( 0: AC AC + MA 1: M[A] AC, AC  0 2: M[A] M[A]+ 1, IF M[A]= 0 THEN PC  PC + 1 3: PC  A ...................................... 7: IF F0 THEN AC  AC + 1 IF F1 THEN IF AC = 0 THEN PC  PC + 1 IF F2 THEN (TMP  AC, AC  AX, AX  TM’) END END

  30. DD Synthesis from Behavioral Descriptions Symbolic execution tree: Start OP=7 OP=0 ... F0=1 1 OP=3 F0=0 AC = AC + 1 AC = AC + M [A] OP=1 PC = A F1=1 F1=0 2 OP=2 AC0 5 AC=0 M [A] = AC, AC = 0 F2=0 PC = PC + 1 F2=0 6 F2=0 F2=1 F2=1 11 M [A] = M [A] + 1 F2=1 9 M[A]=0 3 AC = AX, AX = AC M[A]=1 AC = AX, AX = AC PC = PC + 1 7 AC = AX, AX = AC 10 4 8

  31. DD Synthesis from Behavioral Descriptions Generation of nonprocedural descriptions via symbolic execution Terminal contexts

  32. DD Synthesis from Behavioral Descriptions Decision Diagram for AC 0 AC+M [A] AC OP 1 #0 2,3 AC 7 0 0 F0 F2 1 1 AX AC+1

  33. Data Path M A ADR B C z 1 MUX 1 z CC z 2 MUX 2 y x CON D Control Path d l / ¢ q q FF High-Level Decision Diagrams DD-model for a digital system: Digital system:

  34. Begin s 0 A = B + C s 1 1 0 x A Ø A = A + 1 B = B + C s s 4 2 1 0 0 1 x x A B Ø Ø Ø C = C B = B C = C s 3 0 1 0 1 x x C C Ø Ø A = C + B A = A + B + C C = A + B s 5 END High-Level Decision Diagrams DD-model for a digital system: Digital system:

  35. I1: MVI A,D A  IN I2: MOV R,A R  A I3: MOV M,R OUT  R I4: MOV M,A OUT  A I5: MOV R,M R  IN I6: MOV A,M A  IN I7: ADD R A  A + R I8: ORA R A  A  R I9: ANA R A  A  R I10: CMA A,D A  A Test Generation for Processors High-Level DDs for a microprocessor (example): DD-model of the microprocessor: Instruction set: 1,6 A I IN 3 2,3,4,5 I R OUT A 4 7 A + R A 8 2 A  R I A R 9 A  R 5 IN 10  A 1,3,4,6-10 R

  36. Test Generation for Processors High-Level DD-based structureofthe microprocessor (example): DD-model of the microprocessor: 1,6 A I IN IN 3 R 2,3,4,5 I R OUT A 4 7 A + R I A OUT 8 2 A  R I A R 9 A  R 5 A IN 10  A 1,3,4,6-10 R

  37. Test Generation for Processors Scanning test program for adder: Instruction sequence T = I5 (R)I1 (A)I7 I4 for all needed pairs of (A,R) DD-model of the microprocessor: 1,6 A I IN I4 3 OUT 2,3,4,5 I R OUT A I7 A 4 7 A + R I1 A A 8 R IN(2) 2 A  R I A R I5 R 9 A  R 5 IN(1) IN Time: 10 t t - 1 t - 2 t - 3  A 1,3,4,6-10 Observation Test Load R

  38. Test Generation for Processors Conformity test program for decoder: Instruction sequence T = I5 I1 DI4 for all DI1 -I10 at given A,R,IN DD-model of the microprocessor: 1,6 I A IN Data generation: 3 2,3,4,5 I R OUT A 4 7 A + R A 8 2 A  R I A R 9 A  R 5 IN 10  A 1,3,4,6-10 Data IN,A,R are generated so that the values of all functions were different R

  39. Vector Decision Diagrams Vector Decision Diagrams: 0 A 0 0 C ¢ B’ + C’ q M=A.B.C.q i ¢ q x A’ + B’ ¢ ¢ q B + C i A B q #1 1 0 #5 x Ø ¢ A + 1 A 1 0 A 1 C Ø x A’ + 1 i 3 1 A Ø i C’ q x q Ø ¢ ¢ C + B C #4 #3 4 0 0 1 B x x ¢ ¢ ¢ A + B + C C A B’ + C’ 0 0 A i q x x A’ + B’+C’ i A C 1 1 B #2 2 x ¢ ¢ ¢ B + C q B Ø B’ A q 4 0 #5 3 0 C 0 x Ø ¢ B A’ + B’ x ¢ q # A q 1 i B C q Ø B’ i 2 0 1 0 #5 q x ¢ x # q ¢ ¢ 4 A + B C B A #5 1 A 1 Ø B’ + C’ 1 3 i 0 1 C q x # 2 Ø C’ i C #5 q 4 0 2 4 1 #5 x # 5 x B Ø ¢ C A 1 3,4 # 3 Concurrent simulation in space: j – adressing variable

  40. Two-Dimensional Decision Diagrams DDs for representing microprocessor output behaviour A 1 OUT = AB.DB (t) AB 2 i PC + 1 0 1 1 t I I 1 3 AB 3 i PC + 2 1 A 2 DB L PC + 1 DB(t=2) 2 0, 2 2 t I i i INP (H,L) 2 1 2 AB PC + 2 H DB(t=3) AB SHLD Instruction: 1, 3 2 t i I .I .I = 0.4.2 1 1 2 3 Concurrent simulation: in space: i – adressing variable in time: t – adressing variable ¬ (DB(t=3).DB(t=2)) L 2 4 t A 1 ¬ ((DB(t=3).DB(t=2)) + 1) H 3 A 2 DB i 4 L I I I i 1 2 3 1 0 1 2 4 5 7 AB INP space DB H 5 i time 1 t AB INP + 1

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