1 / 3

Final Exam (Exam 3) Information

Final Exam (Exam 3) Information. Tues., May 17 th 1 – 2:50 exam written for ~ 1.5 hr length 15% of final grade Mostly short answer Short Verilog examples State Diagrams etc. Open book/notes Calculator is ok. Logistics. Finite State Machines diagrams encoding/design process

andren
Télécharger la présentation

Final Exam (Exam 3) Information

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Final Exam (Exam 3) Information

  2. Tues., May 17th 1 – 2:50 exam written for ~ 1.5 hr length 15% of final grade Mostly short answer Short Verilog examples State Diagrams etc. Open book/notes Calculator is ok Logistics

  3. Finite State Machines diagrams encoding/design process flip-flop level design Moore vs. Mealy Verilog for FSM naming states separation of combinational and sequential blocks State Machine Minimization process for detecting redundancy in FSMs Coverage • Clocking • Clock skew and distribution • setup and hold time constraints • Synchronization • Avoiding metastability • (synchronizers) • Debouncing inputs • Controlling pulse widths • Memories • Basics of: • SRAM • DRAM • Compare/contrast • Implementation • FPGAs/CPLDs

More Related