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C6000 体系结构和汇编语言

C6000 体系结构和汇编语言. Why DSP?. DSP: Algorithm driven. What kind of Algorithm?. 对大量数据作 相同的运算. 单周期指令； 硬件乘法器； 寻址……. 典型 DSP 算法： 乘法累加 。 For 循环， 20%－80%现象. 时间上： 压缩. DSP 就是为了缩短这样类型的运算的时间， DSP 是如何做到的呢？. 空间上： 并行. 哈佛总线结构； 多运算单元； 流水线……. Learning Objectives.

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C6000 体系结构和汇编语言

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  1. C6000 体系结构和汇编语言

  2. Why DSP? DSP: Algorithm driven What kind of Algorithm? 对大量数据作 相同的运算 单周期指令； 硬件乘法器； 寻址…… 典型DSP算法： 乘法累加 。 For循环， 20%－80%现象 时间上： 压缩 DSP就是为了缩短这样类型的运算的时间，DSP是如何做到的呢？ 空间上： 并行 哈佛总线结构； 多运算单元； 流水线……

  3. Learning Objectives • Describe C6000 CPU architecture. • Introduce instructions by an example

  4. General DSP System Block Diagram External Memory Internal Memory Internal Buses PERIPHERALS Central Processing Unit

  5. C6000 CPU Architecture VLIW, Very Long Instruction word

  6. 对比：TigerShare101 Architecture

  7. C6201/04/05 片内存储器

  8. C6701片内存储器

  9. C64x 片内2级存储器 C64的 L1D的存储体结构：8×32bit。（32B） L1D行：64B。共128组（4K字）

  10. 片外存储器 片内存储器 数据寄存器 处理 单元 程序员角度的DSP结构：存储器的层次

  11. C62xx CPU Core

  12. C67xx CPU Core

  13. C64xx CPU Core

  14. 一条C6000的指令和其机器码 • C6000: ADD .D2 B5,B4,B4 ADD (.D2 or.D1) src2,src1,dst1 • 00000010000101001000100001000010 • 000 0 00100 00101 00100 010000 10000 1 0 • (1) (2) (3) （4） (5) （6） （7）（8）（9） • (1)  条件寄存器: A1,A2,B0~2; C64添加A0 • (2)  z，指定条件寄存器的判断条件 • (3)  dst，目的 • (4)  src2，源2 • (5)  src1, 源1 • (6)  操作码：设定唯一指令的码，sint，2个源和目标都为有符号整数且功能单元为D时的操作码就是010000 ； • (7)  固定值 • (8)  s，选择A边寄存器还是B边寄存器 • (9) p，是否并行

  15. 对比：8086的ADD指令 8086/8088 一条指令长1~6字节 8086 ADD CX,DX CX和DX相加放到CX 000000 0 1 11 001 010；寻址方式和立即数，这里没有 ADD (1) (2) (3) （4）（5） （1）0 reg为目的， （2）1 字处理（8086的字为16bit）, 表示操作的是CX,DX不是CL,DL。 （3）11，寄存器模式，和 001, 010,一起表示是CX和DX （4）CX, （2）（3）和001一起决定是CX （5）DX, （2）（3）和010一起决定是DX

  16. N Two basic operations are required for this algorithm. (1) Multiplication (2) Addition Therefore two basic instructions are required • anxn Y = * n = 1 = a1* x1 + a2 * x2+... + aN *xN Implementation of Sum of Products (SOP) SOP is the key element for most DSP algorithms. So let’s write the code for this algorithm and at the same time learn the C6000 architecture.

  17. N • anxn Y = * n = 1 Implementation of Sum of Products (SOP) So let’s implement the SOP algorithm! The implementation in this module will be done in assembly. Two basic operations are required for this algorithm. (1) Multiplication (2) Addition Therefore two basic instructions are required = a1* x1 + a2 * x2+... + aN *xN

  18. N • anxn Y = * n = 1 Multiply (MPY) = a1* x1 + a2 * x2+... + aN *xN The multiplication of a1 by x1 is done in assembly by the following instruction: MPY a1, x1, Y This instruction is performed by a multiplier unit that is called “.M”

  19. 40 • an xn Y = * n = 1 Multiply (.M unit) .M The . M unit performs multiplications in hardware MPY .M a1, x1, Y Note: 16-bit by 16-bit multiplier provides a 32-bit result. 32-bit by 32-bit multiplier provides a 64-bit result.

  20. 40 • an xn Y = * n = 1 Addition (.?) .M MPY .M a1, x1, prod ADD .? Y, prod, Y .?

  21. 40 • an xn Y = * n = 1 Add (.L unit) .M MPY .M a1, x1, prod ADD .L Y, prod, Y .L RISC processors such as the C6000 use registers to hold the operands, so lets change this code.

  22. 40 • an xn Y = * Register File A n = 1 A0 A1 A2 A3 A4 A15 a1 x1 .M prod Y .L ... 32-bits Register File - A MPY .M a1, x1, prod ADD .L Y, prod, Y Let us correct this by replacing a, x, prod and Y by the registers as shown above.

  23. 40 • an xn Y = * Register File A n = 1 A0 A1 A2 A3 A4 A15 a1 x1 .M prod Y .L ... 32-bits Specifying Register Names MPY .M A0, A1, A3 ADD .L A4, A3, A4 The registers A0, A1, A3 and A4 contain the values to be used by the instructions.

  24. 40 • an xn Y = * Register File A n = 1 A0 A1 A2 A3 A4 A15 a1 x1 .M prod Y .L ... 32-bits Specifying Register Names MPY .M A0, A1, A3 ADD .L A4, A3, A4 Register File A contains 16 registers (A0 -A15) which are 32-bits wide.

  25. Register File A A0 A1 A2 A3 A4 A15 a1 x1 .M prod Y .L ... 32-bits Data loading Q: How do we load the operands into the registers?

  26. Register File A A0 A1 A2 A3 A15 a1 x1 .M prod Y .L ... .D 32-bits Data Memory Load Unit “.D” Q: How do we load the operands into the registers? A: The operands are loaded into the registers by loading them from the memory using the .D unit.

  27. Register File A A0 A1 A2 A3 A15 a1 x1 .M prod Y .L ... .D 32-bits Data Memory Load Unit “.D” It is worth noting at this stage that the only way to access memory is through the .D unit.

  28. Register File A A0 A1 A2 A3 A15 a1 x1 .M prod Y .L ... .D 32-bits Data Memory Load Instruction Q: Which instruction(s) can be used for loading operands from the memory to the registers?

  29. Register File A A0 A1 A2 A3 A15 a1 x1 .M prod Y .L ... .D 32-bits Data Memory Load Instructions (LDB, LDH,LDW,LDDW) Q: Which instruction(s) can be used for loading operands from the memory to the registers? A: The load instructions.

  30. Using the Load Instructions Before using the load unit you have to be aware that this processor is byte addressable, which means that each byte is represented by a unique address. Also the addresses are 32-bit wide. Data address 00000000 00000002 00000004 00000006 00000008 FFFFFFFF 16-bits

  31. Using the Load Instructions The syntax for the load instruction is: Where: Rn is a register that contains the address of the operand to be loaded and Rm is the destination register. Data address 00000000 a1 00000002 x1 LD *Rn,Rm 00000004 00000006 prod Y 00000008 FFFFFFFF 16-bits

  32. Using the Load Instructions The syntax for the load instruction is: The question now is how many bytes are going to be loaded into the destination register? Data address 00000000 a1 00000002 x1 LD *Rn,Rm 00000004 00000006 prod Y 00000008 FFFFFFFF 16-bits

  33. LD *Rn,Rm Using the Load Instructions The syntax for the load instruction is: Data address 00000000 a1 00000002 x1 00000004 00000006 prod The answer, is that it depends on the instruction you choose: • LDB: loads one byte (8-bit) • LDH: loads half word (16-bit) • LDW: loads a word (32-bit) • LDDW: loads a double word (64-bit) Note: LD on its own does not exist. Y 00000008 FFFFFFFF 16-bits

  34. LD *Rn,Rm Using the Load Instructions Data The syntax for the load instruction is: address 1 0 0xA 0xB 00000000 0xC 0xD 00000002 0x2 0x1 00000004 0x4 0x3 00000006 Example: If we assume that A5 = 0x4 then: (1) LDB *A5, A7 ; gives A7 = 0x00000001 (2) LDH *A5,A7; gives A7 = 0x00000201 (3) LDW *A5,A7; gives A7 = 0x04030201 (4) LDDW *A5,A7:A6; gives A7:A6 = 0x0807060504030201 0x6 0x5 00000008 0x8 0x7 FFFFFFFF 16-bits

  35. LD *Rn,Rm Using the Load Instructions The syntax for the load instruction is: Data address 0xA 0xB 00000000 0xC 0xD 00000002 0x2 0x1 00000004 0x4 0x3 00000006 Question: If data can only be accessed by the load instruction and the .D unit, how can we load the register pointer Rn in the first place? 0x6 0x5 00000008 0x8 0x7 FFFFFFFF 16-bits

  36. The instruction MVKL will allow a move of a 16-bit constant into a register as shown below: MVKL .? a, A5 (‘a’ is a constant or label) • How many bits represent a full address? 32 bits • So why does the instruction not allow a 32-bit move? All instructions are 32-bit wide (see instruction opcode). Loading the Pointer Rn

  37. ah al a ah x A5 Loading the Pointer Rn • To solve this problem another instruction is available: MVKH eg.MVKH .? a, A5 (‘a’ is a constant or label) • Finally, to move the 32-bit address to a register we can use: MVKL a, A5 MVKH a, A5

  38. Loading the Pointer Rn • Always use MVKL then MVKH, look at the following examples: Example 1 A5 = 0x87654321 MVKL 0x1234FABC, A5 A5 = 0xFFFFFABC (sign extension) MVKH 0x1234FABC, A5 A5 = 0x1234FABC ; OK Example 2 MVKH 0x1234FABC, A5 A5 = 0x12344321 MVKL 0x1234FABC, A5 A5 = 0xFFFFFABC ; Wrong

  39. MVKL pt1, A5 MVKH pt1, A5 MVKL pt2, A6 MVKH pt2, A6 LDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 Register File A A0 A1 A2 A3 A15 a x .M prod Y .L ... .D 32-bits Data Memory LDH, MVKL and MVKH

  40. Creating a loop MVKL pt1, A5 MVKH pt1, A5 MVKL pt2, A6 MVKH pt2, A6 LDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 So far we have only implemented the SOP for one tap only, i.e. Y= a1* x1 So let’s create a loop so that we can implement the SOP for N Taps.

  41. Creating a loop So far we have only implemented the SOP for one tap only, i.e. Y= a1* x1 So let’s create a loop so that we can implement the SOP for N Taps. With the C6000 processors there are no dedicated instructions such as block repeat. The loop is created using the B instruction.

  42. What are the steps for creating a loop 1. Create a label to branch to. 2. Add a branch instruction, B. 3. Create a loop counter. 4. Add an instruction to decrement the loop counter. 5. Make the branch conditional based on the value in the loop counter.

  43. MVKL pt1, A5 MVKH pt1, A5 MVKL pt2, A6 MVKH pt2, A6 loop LDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 1. Create a label to branch to

  44. MVKL pt1, A5 MVKH pt1, A5 MVKL pt2, A6 MVKH pt2, A6 loop LDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 B .? loop 2. Add a branch instruction, B.

  45. MVKL pt1, A5 MVKH pt1, A5 MVKL pt2, A6 MVKH pt2, A6 loopLDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 B .? loop Register File A A0 A1 A2 A3 A15 a x .M prod Y .L ... 32-bits Which unit is used by the B instruction? Register File A .S A0 A1 A2 A3 A15 a x .M prod Y .L ... .D .D 32-bits Data Memory

  46. MVKL .S pt1, A5 MVKH .S pt1, A5 MVKL .S pt2, A6 MVKH .S pt2, A6 loopLDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 B .S loop Register File A A0 A1 A2 A3 A15 a x .M prod Y .L ... 32-bits Which unit is used by the B instruction? Register File A .S A0 A1 A2 A3 A15 a x .M prod Y .L ... .D .D 32-bits Data Memory

  47. MVKL .S pt1, A5 MVKH .S pt1, A5 MVKL .S pt2, A6 MVKH .S pt2, A6 MVKL .S count, B0 loopLDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 B .S loop Register File A A0 A1 A2 A3 A15 a x .M prod Y .L ... 32-bits 3. Create a loop counter. Register File A .S A0 A1 A2 A3 A15 a x .M prod Y .L ... .D .D 32-bits B registers will be introduced later Data Memory

  48. MVKL .S pt1, A5 MVKH .S pt1, A5 MVKL .S pt2, A6 MVKH .S pt2, A6 MVKL .S count, B0 loopLDH .D *A5, A0 LDH .D *A6, A1 MPY .M A0, A1, A3 ADD .L A4, A3, A4 SUB .S B0, 1, B0 B .S loop Register File A A0 A1 A2 A3 A15 a x .M prod Y .L ... 32-bits 4. Decrement the loop counter Register File A .S A0 A1 A2 A3 A15 a x .M prod Y .L ... .D .D 32-bits Data Memory

  49. 5. Make the branch conditional based on the value in the loop counter • What is the syntax for making instruction conditional? [condition] Instruction Label e.g. [B1] B loop (1) The condition can be one of the following registers: A1, A2, B0, B1, B2. (2) Any instruction can be conditional.

  50. 5. Make the branch conditional based on the value in the loop counter • The condition can be inverted by adding the exclamation symbol “!” as follows: [!condition] Instruction Label e.g. [!B0] B loop ;branch if B0 = 0 [B0] B loop ;branch if B0 != 0

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