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PPI

PPI. Programmable Peripheral Interface Parallel port Interface 8255. 8255 PPI. Addressing the 8255. A1 A0 = 00 Port A ; IN, OUT 8 bits at a time = 01 Port B ; IN, OUT 8 bits at a time = 10 Port C ; IN, OUT 8 bits at a time = 11 Control Register; Write ONLY!. Addressing Example

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PPI

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  1. PPI Programmable Peripheral Interface Parallel port Interface 8255

  2. 8255 PPI

  3. Addressing the 8255 A1 A0 = 00 Port A ; IN, OUT 8 bits at a time = 01 Port B ; IN, OUT 8 bits at a time = 10 Port C ; IN, OUT 8 bits at a time = 11 Control Register; Write ONLY! Addressing Example PORTA EQU 0224h ;Port A 8255 PORTB EQU 0225h ;Port B 8255 PORTC EQU 0226h ;Port C 8255 STAT EQU 0227h ;Control Port Another Addressing Example A2A1(CPU)A1A0(PPI) PORTA EQU 0224h ;Port A 8255 PORTB EQU 0226h ;Port B 8255 PORTC EQU 0228h ;Port C 8255 STAT EQU 022ah ;Control Port

  4. Address Only A19 A18 A17 A16 Address/Data AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 Address and Data lines are multiplexed in the 8086 + Interfacing the 8255 20 8086 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

  5. ALE ALE is Address Latch Enable Address and Data Buses 20 8086 Address Latch 20-bit address bus 16 Data Transceiver 16-bit data bus

  6. IO/M 8 8 4 4 Data Port A Port B RESET { CH A15 -A2 Logic Circuit CS WR RD Port C CL A1 A0 Addressing the 8255 8-bit data bus 20-bit address bus A1 A0

  7. Logic Circuit • Inputs to the Logic Circuit • address lines A15 - A2(the I/0 address space is 216 addresses, and A1 and A0 are used for the chip’s address lines) • the 8086’s IO/M lineHIGH denotes an IO instruction (IN, OUT)LOW denotes a memory access instruction (i.e., MOV) • Output of the logic circuit • a single low value from the 15 inputs (a NAND or OR gate) to activate the Chip Select • The connections for A15-A2 fix the chip’s address in I/O space

  8. 8 address/data lines 12 addresslines IO/M RD and WR 8088 pins The 8088 is a 16-bit microprocessor: Internal registers and buses are 16 bits wide

  9. Minimum mode • In minimum mode, the 8086/8088 is the only microprocessor in the circuit. It can assume that it has control of memory, address, and data buses • In maximum mode, the 8086/8088 is configured for multiple microprocessors. The function of pins is changed to provide processor-to-processor communication

  10. Reset • A single reset line is connected to all chips in the system (8088/8086, 8255, 8253, etc.) • Reset puts the chip in a known state • Pushing the reset button on your computer generally activates RES pin of 8284 that outputs a high Reset pulse for a short period of time • On Reset, the 8088/8086 goes to fixed addresses (ROM chips) where boot sequence instructions are stored.

  11. Basic Description of the 8255 • Its three I/O ports (labeled A,B, and C) are programmed in groups of 12 pins : • Group A connections consist of port A (PA7-PA0) and the upper half of port C (PC7-PC4) • Group Bconsists of port B (PB7-PB0) and the lower half of port C(PC3-PC0) • The 8255 is selected by its CS pin for programming, for reading or writing to a port. • Register selection is accomplished through the A1 and A0 input pins, which select an internal register for programming or operation

  12. 8255A PPI – Parallel I/O Interface

  13. 8255A PPI – Assets and Capabilities • 24 I/O lines in 3 8-bit port groups – A, B, C • A, B can be 8-bit input or output ports • C can serve as 2 4-bit input or output ports • 3 modes of operation: • Mode 0: A, B, C simple input or output level sensitive ports • Mode 1: A, B input or output ports with strobe control in C • Mode 2: A is bidirectional with control/handshake in B and C • A, B can only change 1 byte at a time • C has individual bit set/reset capability Advantage is non-dedicated circuit can change portconfiguration with software and no “glue logic”

  14. Mode Selection of the 8255 • Ports A, B, and C are used for I/O data. • The control register is programmed to select the operation mode of the three ports A, B, and C. • Mode 0 : simple I/O mode • Any of the ports A, B, CL and CU can be programmed as input or output. • No control of individual bits (all bits are out or all bits are in) • Mode 1 : Ports A and B can be used as input or output ports with handshaking. • Mode 2 : Port A can be used as bidirectional I/O port with handshaking

  15. PPI Interface to CPU the PPI maps each of its 4 bytes to an address, but all connect to the same byte of the data bus; if data bus is 1 byte wide, they are consecutive addresses; if the bus is 2 bytes wide, they are mapped to alternate addresses; if the bus is 4 bytes wide, …etc.

  16. Programming/Controlling the PPI • 8255A PPI has a “write-only” control register, accessed when PPI’s A0=A1=1 (note: notA0 and A1 of the address bus!) • When PPI is reset (by an active-high strobe on its RESET pin): • Default is A, B, C are mode 0 input ports • Control register also used to set/reset port C bits individually

  17. PPI Programming Example ; Assume address decoder designed for PPI base address 0400h ; PPI is connected to D7-D0 on CPU data bus mov dh, 04h mov dl, 01h mov al, 82h out dx, al What does the code shown above do????

  18. Control Word Example ;Assume address decoder designed for PPI base address 0400h ;PPI connected to D7-D0 on CPU data bus mov dh, 04h ;Let dh point to base address mov dl, 03h ;Select the control register mov al, 82h ;Place 82h Control Word into al out dx, al ;Write al contents to PPI ;explanation of operating mode set by this code ; D7=1 Control Word (not a bit set/reset command) ; D6D5=00 A and C7-C4 are Mode 0 (Group A) ; D4=0 A is Level Sensitive Output ; D3=0 C7-C4 are Level Sensitive Output ; D2=0 B and C3-C0 are Mode 0 (Group B) ; D1=1 B is Level Sensitive Input ; D0=0 C3-C0 are Level Sensitive Output

  19. 8255 Connection to Stepper Motor

  20. HW#2 • Sketch the schematic diagram for a 8086 minimum system that drives 8 seven segments through a PPI. • PortA of PPI serves as the driver for the segments of a digit. (PA0=a, PA1=b,..,PA6=g, PA7=‘.’; • PortB of PPI serves as the digit selection • Develop the SCAN Program. • Input: AL (0 to 7) the digit that should be shown • This routine is called every 10 ms • Due Date: Sunday 22 Farvardin 1389

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