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Lecture 5. MIPS Processor Design Pipelined MIPS #1

COMP212 Computer Architecture. Lecture 5. MIPS Processor Design Pipelined MIPS #1. Prof. Taeweon Suh Computer Science Education Korea University. Processor Performance. Performance of single-cycle processor is limited by the long critical path delay

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Lecture 5. MIPS Processor Design Pipelined MIPS #1

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  1. COMP212 Computer Architecture Lecture 5. MIPS Processor Design Pipelined MIPS #1 Prof. Taeweon Suh Computer Science Education Korea University

  2. Processor Performance • Performance of single-cycle processor is limited by the long critical path delay • The critical path limits the operating clock frequency • Can we do better? • New semiconductor technology will reduce the critical path delay by manufacturing with small-sized transistors • Core 2 Duo: 65nm technology • 1st Gen. Core i7 (Nehalem): 45nm technology • 2nd Gen. Core i7 (Sandy Bridge): 32nm technology • 3rd Gen. Core i7 (Ivy Bridge): 22nm technology • Can we increase the processor performance with a different microarchitecture? • Yes! Pipelining

  3. A B C D Revisiting Performance • Laundry Example • Ann, Brian, Cathy, Dave each have one load of clothes to wash, dry, and fold • Washer takes 30 minutes • Dryer takes 40 minutes • Folder takes 20 minutes

  4. A B C D Sequential Laundry 6 PM Midnight 7 8 9 11 10 Time 30 40 20 30 40 20 30 40 20 30 40 20 T a s k O r d e r • Response time: • Throughput: 90 mins 0.67 tasks / hr (= 90mins/task, 6 hours for 4 loads)

  5. 30 40 40 40 40 20 A B C D Pipelining Lessons 6 PM 7 8 9 • Pipelining doesn’t help latency (response time) of a single task • Pipelining helps throughput of entire workload • Multiple tasks operating simultaneously • Unbalanced lengths of pipeline stages reduce speedup • Potential speedup = # of pipeline stages Time T a s k O r d e r • Response time: • Throughput: 90 mins 1.14 tasks / hr (= 52.5 mins/task, 3.5 hours for 4 loads)

  6. P r o g r a m 2 4 6 8 1 0 1 2 1 4 1 6 1 8 e x e c u t i o n T i m e o r d e r ( i n i n s t r u c t i o n s ) I n s t r u c t i o n D a t a l w $ 1 , 1 0 0 ( $ 0 ) R e g A L U R e g f e t c h a c c e s s I n s t r u c t i o n D a t a l w $ 2 , 2 0 0 ( $ 0 ) R e g A L U R e g 8 n s f e t c h a c c e s s I n s t r u c t i o n l w $ 3 , 3 0 0 ( $ 0 ) 8 n s f e t c h . . . 8 n s P r o g r a m 1 4 2 4 6 8 1 0 1 2 e x e c u t i o n T i m e o r d e r ( i n i n s t r u c t i o n s ) I n s t r u c t i o n D a t a l w $ 1 , 1 0 0 ( $ 0 ) R e g A L U R e g f e t c h a c c e s s I n s t r u c t i o n D a t a l w $ 2 , 2 0 0 ( $ 0 ) 2 n s R e g A L U R e g f e t c h a c c e s s I n s t r u c t i o n D a t a l w $ 3 , 3 0 0 ( $ 0 ) 2 n s R e g A L U R e g f e t c h a c c e s s 2 n s 2 n s 2 n s 2 n s 2 n s Pipelining • Improve performance by increasing instruction throughput Sequential Execution Pipelined Execution

  7. I I I I I I n n n n n n s s s s s s t t t t t t r r r r r r u u u u u u c c c c c c t t t t t t i i i i i i o o o o o o n n n n n n D D D D D D a a a a a a t t t t t t a a a a a a R R R R R R e e e e e e g g g g g g A A A A A A L L L L L L U U U U U U R R R R R R e e e e e e g g g g g g f f f f f f e e e e e e t t t t t t c c c c c c h h h h h h a a a a a a c c c c c c c c c c c c e e e e e e s s s s s s s s s s s s Pipelining (Cont.) Pipeline Speedup • If all stages are balanced (meaning that each stage takes the same amount of time) • If not balanced, speedup is less • Speedup comes from increased throughput (the latency of instruction does not decrease) Multiple instructions are being executed simultaneously P r o g r a m 1 4 2 4 6 8 1 0 1 2 e x e c u t i o n T i m e o r d e r ( i n i n s t r u c t i o n s ) I n s t r u c t i o n D a t a l w $ 1 , 1 0 0 ( $ 0 ) R e g A L U R e g f e t c h a c c e s s I n s t r u c t i o n D a t a l w $ 2 , 2 0 0 ( $ 0 ) 2 n s R e g A L U R e g f e t c h a c c e s s I n s t r u c t i o n D a t a l w $ 3 , 3 0 0 ( $ 0 ) 2 n s R e g A L U R e g f e t c h a c c e s s … Time to execute an instructionsequential = Time to execute an instructionpipeline Number of stages

  8. Pipelining and ISA Design • MIPS ISA is designed with pipelining in mind • All instructions are 32-bits (4 bytes) • Compared with x86 (CISC): 1- to 17-byte instructions • Regular instruction formats • Can decode and read registers in one cycle • Load/store addressing • Calculate address in 3rd stage • Access memory in 4th stage • Alignment of memory operands in memory • Memory access takes only one cycle • For example, 32-bit data (word) is aligned at word address • 0x…0, 0x…4, 0x…8, 0x…C

  9. Basic Idea • What should be done to implement pipelining (split into stages)?

  10. Basic Idea clock F/F F/F F/F F/F

  11. MEM IF ID EX WB add Graphically Representing Pipelines • Shading indicates the unit is being used by the instruction • Shading on the right halfof the register file (ID or WB) or memory means the element is being read in that stage • Shading on the left halfmeans the element is being written in that stage 2 4 6 8 10 Time lw MEM IF ID EX WB

  12. Hazards • It would be happy if we split the datapath into stages and the CPU works just fine • But, things are not that simple as you may expect • There are hazards! • Hazard is a situation that prevents starting the next instruction in the next cycle • Structure hazards • Conflict over the use of a resource at the same time • Data hazard • Data is not ready for the subsequent dependent instruction • Control hazard • Fetching the next instruction depends on the previous branch outcome

  13. Structure Hazards • Structural hazard is a conflict over the use of a resource at the same time • Suppose the MIPS CPU with a single memory • Load/store requires data access in MEM stage • Instruction fetch requires instruction access from the same memory • Instruction fetch would have to stall for that cycle • Would cause a pipeline “bubble” • Hence, pipelined datapaths require either separate ports to memory or separate memories for instruction and data Address Bus Memory MIPS CPU MIPS CPU Address Bus Memory Data Bus Address Bus Data Bus Data Bus

  14. MEM MEM MEM IF IF IF ID ID ID EX EX EX WB WB WB Structure Hazards (Cont.) 2 4 6 8 10 Time lw MEM IF ID EX WB add sub add Either provide separate ports to access memory or provide instruction memory and data memory separately

  15. Data Hazards • Data is not ready for the subsequent dependent instruction MEM IF ID EX WB add $s0,$t0,$t1 Bubble Bubble sub $t2,$s0,$t3 MEM IF ID EX WB • To solve the data hazard problem, the pipeline needs to be stalled (typically referred to as “bubble”) • Then, the performance is penalized • A better solution? • Forwarding (or Bypassing)

  16. Forwarding MEM IF ID EX WB add $s0,$t0,$t1 Bubble Bubble MEM IF ID EX WB sub $t2,$s0,$t3

  17. MEM EX WB Data Hazard - Load-Use Case • Can’t always avoid stalls by forwarding • Can’t forward backward in time! • Hardware interlock is needed for the pipeline stall MEM IF ID EX WB lw $s0, 8($t1) Bubble IF ID sub $t2,$s0,$t3 • This bubble can be hidden by proper instruction scheduling

  18. Code Scheduling to Avoid Stalls • Reorder code to avoid use of load result in the next instruction A = B + E; // B is loaded to $t1, E is loaded to $t2 C = B + F; // F is loaded to $t4 lw $t1, 0($t0) lw $t2, 4($t0) lw $t4, 8($t0) add $t3, $t1, $t2 sw $t3, 12($t0) add $t5, $t1, $t4 sw $t5, 16($t0) lw $t1, 0($t0) lw $t2, 4($t0) add $t3, $t1, $t2 sw $t3, 12($t0) lw $t4, 8($t0) add $t5, $t1, $t4 sw $t5, 16($t0) stall stall 11 cycles 13 cycles

  19. Control Hazard • Branch determines the flow of instructions • Fetching the next instruction depends on the branch outcome • Pipeline can’t always fetch correct instruction • Branch instruction is still working on ID stage when fetching the next instruction Taken target address is known here Branch is resolved here MEM MEM MEM IF IF IF ID ID ID EX EX EX WB WB WB beq $1,$2,L1 Bubble add $1,$2,$3 Bubble sw $1, 4($2) … L1: sub $1,$2, $3 MEM IF ID EX WB Fetch the next instruction based on the comparison result

  20. Reducing Control Hazard • To reduce 2 bubbles to 1 bubble, add hardware in ID stage to compare registers (and generate branch condition) • But, it requires additional forwarding and hazard detection logic – Why? Taken target address is known here Branch is resolved here MEM MEM IF IF ID ID EX EX WB WB beq $1,$2,L1 Bubble add $1,$2,$3 … L1: sub $1,$2, $3 MEM IF ID EX WB Fetch instruction based on the comparison result

  21. Delayed Branch • Many CPUs adopt a technique called the delayed branch to further reduce the stall • Delayed branch always executes the next sequential instruction • The branch takes place after execution of the next instruction • Delay slot is the slot right after delayed branch instruction Taken target address is known here Branch is resolved here MEM MEM IF IF ID ID EX EX WB WB beq $1,$2,L1 (delay slot) add $1,$2,$3 … L1: sub $1,$2, $3 MEM IF ID EX WB Fetch instruction based on the comparison result

  22. Delay Slot (Cont.) • Compiler needs to schedule a useful instruction in the delay slot, or fills it up with nop (no operation) // $s1 = a, $s2 = b, $3 = c // $t0 = d, $t1 = f a = b + c; if (d == 0) {f = f + 1;} f = f + 2; add $s1,$s2, $s3 bne $t0,$zero, L1 nop //delay slot addi $t1, $t1, 1 L1: addi $t1, $t1, 2 Can we do better? bne $t0, $zero, L1 add $s1,$s2,$s3 // delay slot addi $t1, $t1, 1 L1: addi $t1, $t1, 2 Fill the delay slot with a useful and valid instruction

  23. Branch Prediction • Longer pipelines (for example, Core 2 Duo has 14 stages) can’t readily determine branch outcome early • Stall penalty becomes unacceptable since branch instructions are used so frequently in the program • Solution: Branch Prediction • Predict the branch outcome in hardware • Flush the instructions (that shouldn’t have been executed) in the pipeline if the prediction turns out to be wrong • Modern processors use sophisticated branch predictors • Our MIPS implementation is like branches-not-taken prediction (with no delayed branch) • Fetch the next instruction after branch • If the prediction turns out to be wrong, flush out the instruction fetched

  24. MIPS with Predict-Not-Taken Prediction correct Flush the instruction that shouldn’t be executed Prediction incorrect

  25. Pipeline Summary • Pipelining improves performance by increasing instruction throughput • Executes multiple instructions in parallel • Pipelining is subject to hazards • Structure hazard • Data hazard • Control hazard • ISA affects the complexity of the pipeline implementation

  26. Backup Slides

  27. Past, Present, Future (Intel) Source: http://en.wikipedia.org/wiki/Sandy_Bridge

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