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CLEO-III Trigger & DAQ Status

CLEO-III Trigger & DAQ Status. Trigger Illinois (Cornell). DAQ OSU Caltech Cornell. 72 MHz. RF bucket. 24 MHz. Pipeline clk. Early DR. Late DR. Early CC. Late CC. look here for DR info. look here for CC info. Suppose event happens here. CLEO-III Trigger. Trigger Philosophy

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CLEO-III Trigger & DAQ Status

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  1. CLEO-III Trigger & DAQ Status Trigger Illinois (Cornell) DAQ OSU Caltech Cornell CLEO PAC 11/March/00 M. Selen, University of Illinois

  2. 72 MHz RF bucket 24 MHz Pipeline clk Early DR Late DR Early CC Late CC look here for DR info look here for CC info Suppose eventhappens here CLEO-III Trigger Trigger Philosophy • Make a sophisticated Level-1 trigger decision (latency~2.5ms) before invoking readout dead-time. • Make trigger decision every 42ns (i.e. pipeline). At L = 3 x 1033 this corresponds to ~250 Hz. Design CLEO-III trigger/DAQ for 1000 Hz max. CLEO PAC 11/March/00 M. Selen, University of Illinois

  3. TRCR TIM DM/CTL TIM DM/CTL CLEO-III Trigger: System Inventory Mixer/Shaper Crates (24) Drift Chamber Crates Gates CLEO Mixer/Shaper Boards Contr. DR3 Pre-amps G / CAL Analog TILE (8) AXTR(16) AXX(16) DFC DAQ Flow control & Gating Barrel CC QVME TIM TIM Axial tracker DM/CTL DM/CTL TILE (8) Patch panel Barrel CC QVME L1LUMI STTR(12) L1D Stereo tracker TILE (8) L1D TIM Endcap CC QVME DM/CTL Level 1 decision AXPR TCTL CCGL TPRO(4) SURF TPRO(2) SURF CC Digital CLEO PAC 11/March/00 M. Selen, University of Illinois

  4. VME/DAQ Interface Trigger Logic Custom BP Trigger Hardware Example Example (they all look similar):Level-1 Trigger Decision Board CLEO PAC 11/March/00 M. Selen, University of Illinois

  5. Common Trigger Board Structure Inputs FPGA based Logic Outputs Circular Buffer DAQ/ VME TDI TMS TCK TDO JTAG CLEO PAC 11/March/00 M. Selen, University of Illinois

  6. Stereo (blocks) Axial(all wires) Tracking Trigger (Axial + Stereo) CLEO PAC 11/March/00 M. Selen, University of Illinois

  7. #tracks time ev-time Finding the Event Time 2 trackEvents Trigger Bucket CLEO PAC 11/March/00 M. Selen, University of Illinois

  8. contained shower Simulated Efficiency Present summing = Tile summing = CC Trigger Energy sharing between boards can result in a loss of efficiency: Threshold = 500 MeV CLEO PAC 11/March/00 M. Selen, University of Illinois

  9. Analog “TILE” Boards CLEO PAC 11/March/00 M. Selen, University of Illinois

  10. Preliminary Peek at the CC Trigger Data Barrel(Crate 1 Card 13) Endcap(Crate 21 Card 16) CLEO PAC 11/March/00 M. Selen, University of Illinois

  11. CC Tile Processor 1 m/s crate   CLEO PAC 11/March/00 M. Selen, University of Illinois

  12. 48 24 24 Route Prescale Bunch LUT 8 FPGAs Info (185) L1-accept Backplane Timing (3) Scaler Info (valid at timing edge) Timing (TR, CB or CE) Level 1 Decision CLEO PAC 11/March/00 M. Selen, University of Illinois

  13. Writing Trigger Lines % Generic Hadron Line, Barrel Timing % SUBDESIGN line0( in[117..0] : INPUT; out : OUTPUT; ) Variable 1cblow : SOFT; 3tracks : SOFT; evtime : SOFT; Begin -- trigger bit mappings: tr_time[1..0] = in[1..0]; cb_time[1..0] = in[3..2]; ce_time[1..0] = in[5..4]; cc_time[1..0] = in[7..6]; tr_n_hi[3..0] = in[11..8]; tr_n_lo[3..0] = in[15..12]; tr_n_ax[3..0] = in[19..16]; tr_lowpos[1..0] = in[21..20]; cb_l_phi[7..0] = in[29..22]; cb_h_phi[7..0] = in[37..30]; cb_low_old[1..0] = in[39..38]; cb_med_old[1..0] = in[41..40]; cb_high_old[1..0] = in[43..42]; ce_low_old[1..0] = in[45..44]; ce_med_old[1..0] = in[47..46]; ce_high_old[1..0] = in[49..48]; cb_n_low[2..0] = in[52..50]; cb_n_med[2..0] = in[55..53]; cb_n_high[2..0] = in[58..56]; ce_n_low[2..0] = in[61..59]; ce_n_med[2..0] = in[64..62]; ce_n_high[2..0] = in[67..65]; bha_theta[7..0] = in[75..68]; cc_spare[15..0] = in[91..76]; cpu_trig[1..0] = in[93..92]; control[23..0] = in[117..94]; ---------------------------------------------- -- trigger line definition 1cblow = cb_n_low[] > 0; 3tracks = (tr_n_hi[]>2) # ((tr_n_hi[]>1)&(tr_n_lo[]>0)) # ((tr_n_hi[]>0)&(tr_n_lo[]>1)) ; evtime = cb_time[0]; out = 1cblow & 3tracks & evtime; End; CLEO PAC 11/March/00 M. Selen, University of Illinois

  14. Trigger Status • All components (except STTR) boards installed and functioning. • Used for collecting engineering run data • Many bugs shaken out (all readout related) • Some minor readout bugs remain, and will be fixed. • Stereo tracking (STTR) boards will be installed by the end of March. • 8 of 12 needed boards tested (and working) as of today, the balance (4 + spares) will be shipped to LNS by the end of next week. • Majority of trigger groups effort turning to software development. • Much already exists (readout, sparsification, board debugging & testing, expert online tools). • More user friendly (GUI) code being developed. • Monte Carlo ~90% finished. CLEO PAC 11/March/00 M. Selen, University of Illinois

  15. CLEO III DAQ Architecture CLEO PAC 11/March/00 M. Selen, University of Illinois

  16. LUTs VME CPU Fastbus Interface Readout Controller VME PowerPC + VxWorks Fastbus VME-Fastbus Interface (FRITZ) CLEO PAC 11/March/00 M. Selen, University of Illinois

  17. CLEO III Slow Control Structure Level 3 Event Builder Crates Run Control Gas CORBA HV Database Beam User Console (Java) Magnet CLEO PAC 11/March/00 M. Selen, University of Illinois

  18. DAQ Status • All key components installed and functioning. • True for both Data Path & Slow Control • 32 PowerPC crate-based CPU’s used “simultaneously” during engineering run! • 8 VME crates reading out the 230000 RICH channels. • 3 VME crates reading out the trigger system. • 2 VME crates reading out the Silicon Vertex System. • 4 FASTBUS crates reading out the CC via FRITZ • 8 FASTBUS crates reading out the DR via FRITZ. • 7 PowerPC’s performed slow control tasks. • Event Builder worked as expected • This is a big deal ! • The system will grow slightly for “complete CLEO-III” data-taking in April • 1 additional VME crate reading out the stereo trigger. • 3 additional VME crates for reading out the silicon. • Stability and “User Friendliness” improving every day. CLEO PAC 11/March/00 M. Selen, University of Illinois

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