Manfred Meyer & IDT & ODT mmeyer@eso

1. Detector Data Acquisition Hardware Designs and Features of NGC (New General Detector Controller) NGC First Light Image 2005 Manfred Meyer & IDT & ODT mmeyer@eso.org Detectors for Astronomy 2009, ESO Garching, 12-16 Okt

2. Acquisition System Overview

3. Acquisition System – Useful Tools When setting up a detector …

4. Monitoring Signals Front Panel Basic Board NGC Two Convert Utility Signal Signal Monitors LED’s Two Clock Monitors Video Monitor Monitor Selection via GUI

5. Acquisition System – Useful Tools Verifying data flow …

6. Video Data Simulator (Four Channel System) Simulated Video Data show Counter Values (Counter is incremented on each Conversion Strobe) Simulated video data show channel numbers One Channel One Channel Simulation Mode Selection via GUI

7. Acquisition System – Video Channels

8. Video Chain

9. High Speed ADC’s

10. Acquisition System – Bias, Clock

11. Low Frequency System Noise with H2RG The Hawaii-2RG array has 4 rows and columns of reference pixels around the array Even though good noise performance is achieved (9.55e RMS) when the reference pixel subtraction is activated, this is not the case if the reference subtraction is switched off. Without reference subtraction the noise measured is increased by a factor of two. In this operating mode the detector system suffers from strong low frequency noise and the readout noise is 19e RMS

12. Measurements on Detector Bias Voltage(Four Video Channels shown) Ceramic Cap TRC = 0.05s • Test with a bias voltage as input to the video chain • Image shows low frequency noise on the bias voltage • ( same input is applied to all four video channels ) One Channel

13. Simple Things ?Detector Bias Generation

14. Detector Bias Cleanup and Resulting Image (All Double Correlated) Tantalum Cap TRC = 1s

15. Detector Clocks

16. Acquisition System - Preamplifier

17. Detector Preamplifier (Single Ended Input)

18. Detector Preamplifier (Differential Input)

19. Acquisition System - Sequencer

20. Sequencer • Most simple design • But : • Detector readout difficult • to set-up • Not user friendly

21. Sequencer (realized in FPGA) Contains read-out patterns Contains read-out patterns start addresses and sequence code to be executed EOP = End of pattern RSP = Read speed REP = Number of Repetitions

22. Sequencer Code Function and Code Interpretation Time (Sequence RAM)

23. Sequencer Example : PICNIC Array Readout All programming in simple syntax and ASCII code Sequence Pattern (Extract)

24. NGC Design and Applications

25. Conventional Approach :Acquisition System (IRACE) PCI Interface Communication and Data Transfer Acquisition Module(s) Sequencer Clock and Bias

26. NGC System New Design Principle : No Parallel Bus Communication and Data Transfers on High Speed Serial Links with 2 GBit/s

27. NGC System in Minimum Configuration:Basic Board, Backplane and Transition Board See Demo Set-up in Council Room

28. NGC System Component : PCI Back-End

29. Back-End • Function is based on the XILINX Virtex Pro FPGA XC2VP7 FF 672 • Back-End PCI is a 64 Bit PCI board • FPGA contains PCI interface to Communication functions DMA data channel Status and Command • Direct interface from FPGA to PCI without glue logic • PCI master and PCI slave are independent • Scatter – Gather DMA implemented • Communication and data transfers all on serial link with RocketIO transceivers • Handshake communication to Front-End • Data rate on one channel between front and back-end ~ 200MByte/s

30. PCI Back-End

31. NGC System Component : Basic Board

32. Front-End Basic Board • Function is based on the XILINX Virtex Pro FPGA XC2VP7 FF 672 • FPGA contains link interface for communication and data transfer with RocketIO transceivers, sequencer, system administration, interface to acquisition, clock and bias, telemetry and monitoring • Four ADC channels ( 16 or 18Bit) • 18 clocks, 20 biases • Telemetry • Monitoring • Data rate on one channel between front-end modules and front to back-end ~ 200MByte • Handshake for communication to back-end • Galvanic isolated trigger input and control outputs

33. Front-End Basic Board Contains everything to read a CMOS sensor or a CCD with up to four video channels 16 or 18 Bit ADC’s Standard 1 MS/s Optional 3 MS/s

34. NGC System Component : 32 Channel Video Board

35. AQ 32 Board

36. AQ 32 Board 32 Video channels 16 or 18 Bit ADC’s Standard 1 MS/s Optional 3 MS/s Double-Correlated Sampling Readout Noise = 6.9 e RMS

37. Applications with NGC Used as the Building Platform

38. AO Interface for Tip/Tilt Correction Application : Copy Science Data to SFPDP Link of Real Time Processing System SPARTA Detector Control done with NGC BE

39. AO Interface for Tip/Tilt Correction All done with standard NGC Back-End Board- only the Firmware was modified

40. Application : Real Time Processing for Interferometry PMC Based Low Latency DMA Channel DFE is controlled by the PCI Back End Data Transfer from DFE to VME PMC for Interferometry Data also routed through to PCI BE for set-up

41. PMC Based Low Latency DMA Channel

42. Application : Communication Channel to/from ASIC Receiver of Science Data from ASIC all mapped on NGC Fiberlink NGC to ASIC

43. NGC to ASIC – Test Set-up

44. NGC to ASIC Image of Bare Mux H2RG

45. NGC High Speed • Eight 40MS/s Pipeline ADC’s • Ten Clocks with Tr/Tf < 5ns • Eight Biases • Telemetry • Clock and Video Monitors • System is modular

46. Fin