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Lecture 8 RTL Design Methodology Transition from Pseudocode & Interface to a Corresponding Block Diagram

This lecture covers the process of transitioning from pseudocode and interface to a corresponding block diagram in RTL design methodology. Topics include the structure of a typical digital system, hardware design with RTL VHDL, steps of the design process, and implementation and testing techniques.

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Lecture 8 RTL Design Methodology Transition from Pseudocode & Interface to a Corresponding Block Diagram

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  1. Lecture 8 RTL Design Methodology Transition from Pseudocode & Interface to a Corresponding Block Diagram

  2. Required reading • P. Chu, FPGA Prototyping by VHDL Examples • Chapter 6, FSMD • S. Brown and Z. Vranesic, Fundamentals of Digital Logic with VHDL Design • Chapter 10.2, Design Examples ECE 448 – FPGA and ASIC Design with VHDL

  3. Structure of a Typical Digital System Data Inputs Control & Status Inputs Control Signals Datapath (Execution Unit) Controller (Control Unit) Status Signals Data Outputs Control & Status Outputs

  4. Hardware Design with RTL VHDL Interface Pseudocode Datapath Controller Block diagram State diagram or ASM chart Block diagram VHDL code VHDL code VHDL code

  5. Steps of the Design Process • Text description • Interface • Pseudocode • Block diagram of the Datapath • Interface with the division into the Datapath and the Controller • ASM chart of the Controller • RTL VHDL code of the Datapath, the Controller, and the Top Unit • Testbench of the Datapath, the Controller, and the Top Unit • Functional simulation and debugging • Synthesis and post-synthesis simulation • Implementation and timing simulation • Experimental testing

  6. Steps of the Design ProcessPracticed in Class Today • Text description • Interface • Pseudocode • Block diagram of the Datapath • Interface with the division into the Datapath and the Controller • ASM chart of the Controller • RTL VHDL code of the Datapath, the Controller, and the Top Unit • Testbench of the Datapath, the Controller, and the Top Unit • Functional simulation and debugging • Synthesis and post-synthesis simulation • Implementation and timing simulation • Experimental testing

  7. Statistics example

  8. Circuit Interface clk done reset n n dout Statistics din 2 dout_mode go

  9. Pseudocode no_1 = no_2 = no_3 = sum = 0 for i=0 to k-1 do sum = sum + din if din > no_1 then no_3 = no_2 no_2 = no_1 no_1 = din elseif (din > no_2) then no_3 = no_2 no_2 = din elseif (din > no_3) then no_3 = din end if end for avr = sum / k

  10. Interface Table

  11. din n n n en1 reset en rst n+m clk A gt1 clk n+m no_1 A>B n esum B n reset en rst clk 1 0 s2 clk sum n+m en2 reset enc en reset en rst rst clk clk clk clk A gt2 no_2 m A>B n n+m n B i 1 0 s3 >> m = k-1 en3 reset en rst clk n A gt3 clk A>B avr no_3 zk n B no_3 no_2 no_1 n n n dout_mode 00 01 10 11 2 n dout Block diagram of the Datapath

  12. Interface with the division into the Datapath and the Controller din dout_mode clk reset go n 2 gt1 gt2 gt3 Datapath Controller zk en1 en2 en3 esum enc s2 s3 n dout done

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