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Parallel Sequence Spread Spectrum (PSSS)

Parallel Sequence Spread Spectrum (PSSS). Andreas Wolf (aw@dw-a.com) Dr. Wolf & Associates. Proliferation of laptops drives WLAN demand Multimedia applications over WLAN Wireless backbones for WLAN Public hotspot networks Use of WLAN in public telecommunication networks.

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Parallel Sequence Spread Spectrum (PSSS)

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  1. Parallel Sequence Spread Spectrum (PSSS) Andreas Wolf (aw@dw-a.com) Dr. Wolf & Associates Andreas Wolf, Dr. Wolf & Associates

  2. Proliferation of laptops drives WLAN demand Multimedia applications over WLAN Wireless backbones for WLAN Public hotspot networks Use of WLAN in public telecommunication networks Higher data rates, i.e. >500 Mbit/s) More efficient spectrum use,i.e. >>2...4 Bit/s/Hz Range, robutness, MP fadingi.e. at least today’s performance Reduced power consumption Overcome technology barriers for further performance growth Low cost Introduction WLAN Challenges (examples) WLAN Opportunities (examples) Andreas Wolf, Dr. Wolf & Associates

  3. PSSS Characteristics Andreas Wolf, Dr. Wolf & Associates

  4. PSSS 31 Eb/N0 versus Pb Coding Gain 5,5 dB(pb = 1e-5) Andreas Wolf, Dr. Wolf & Associates

  5. PSSS 31 Coding Gain 64 QAM 32 QAM 16 QAM 8 QAM 16PSK 8PSK Coding Gain  5,5 dB 4PSK PSSS 31 2PSK pb = 1e-5 Source: John G. Proakis, Digital Communications 4th edition, McGrawHill, Boston et. al. 2001, page 282. Andreas Wolf, Dr. Wolf & Associates

  6. PSSS – Tx Architecture PSSS – PSSS 31, 88 Mbit/s (22MHz channel) PA DAC + Input Data PSSS Encoder • 10-15 dBc lower linearity required • PAPR 6 dB ~ 5 bit, 44 MSPS /2 DAC < 1,000 gates 5 bit, 44 MSPS OFDM – 54 MBit/s (22 MHz channel) PA DAC + Input Data Scrambler Convolutional Encoder Punturer & Bit Interleaver Constellation Mapping IFFT Insert Pilots Add Prefix/GI ~ 12/14 bit, >80 MSPS • PAPR 17 dB /2 DAC e.g. 40,000 gates 12/14 bit, >80 MSPS Digital Analog Andreas Wolf, Dr. Wolf & Associates

  7. PSSS – Rx Architecture (A) Pre-Select Filter PSSS –PSSS 31, 88 Mbit/s (22MHz channel) PSSS Decoder LNA Correlator LPF 62 + Int. & Dump 10-15 dBc lower linearity required 2 transistors + RC Output Data ~ Output Mapping /2 Correlator LPF 62 Int. & Dump 2 transistors + RC PSSS Reference OFDM – 54 MBit/s (22 MHz channel) < 1000 gates, 44 MSPS 124x I&D Pre-Select Filter Carrier Phase and Time Tracking LNA LPF VGA ADC FFT Synchronization Remove CP + Output Data FEQ Remove Pilots De-Interlaver Viterbi Decoder De- Scrambler ~ 10/12 bit, >40 MSPS /2 LPF VGA ADC (complex) 10/12 bit, >40 MSPS e.g. 40,000 gates, >40 MSPS Digital Analog Andreas Wolf, Dr. Wolf & Associates

  8. I & D I & D 2-bit Comp. 2-bit Comp. PSSS – Rx Architecture (B) Pre-Select Filter PSSS – PSSS 31, 88 Mbit/s (22MHz channel) PSSS Decoder LNA Correlator LPF 31 + 10-15 dBc lower linearity required Output Data ~ Output Mapping /2 Correlator LPF 31 PSSS Reference OFDM – 54 MBit/s (20 MHz channel) < 800 gates, 44 MSPS62x I&D + 2-bit Comp. Pre-Select Filter Carrier Phase and Time Tracking LNA LPF VGA ADC FFT Synchronization Remove CP + Output Data FEQ Remove Pilots De-Interlaver Viterbi Decoder De- Scrambler ~ 10/12 bit, >40 MSPS /2 LPF VGA ADC (complex) 10/12 bit, >40 MSPS e.g. 40,000 gates, >40 MSPS Digital Analog Andreas Wolf, Dr. Wolf & Associates

  9. Path to 1 GBit/s WLAN ? Andreas Wolf, Dr. Wolf & Associates

  10. Extensive research as part of Wolf’s academic / research career PhD in 1990:Application of SAW-based convolver for telecommunication testing “Habilitation” in 1992: (“path” to professorship in Germany) Coding techniques for broadband ISDN [ATM] testing Wolf has developed CCF Coding (Cross Correlation Function) as part of his habilitation in 1991 CCF is almost identical to O-QPSK used in IEEE 802.15.4 (but used in ATM) Wolf is named inventor in related Siemens patent (patent now owned by Tektronix) Continued development of CCF together with Prof. Schwetlick in mid/late 1990’s Increase of bit/s/Hz, move to wireless ”Compilation” of PSSS in 2003 PSSS Background Status Origin of the technology • Comprehensive simulations of PSSS • Reference implementation in progress • Physical proof of concept • Reference design, VHDL, bit-identical simulation bench • R&D grant from BMBF (Ministry of Research & Education, Germany) • Prototype implementation, benchmarking • Pursuing multiple partnering opportunities • Gigabit WLAN (Europe) • WLL (Asia) • Low data rate (100 Kbit/s, 4 bit/s/Hz) Limitation ? • Coherence length of signal in PSSS effectively limits the maximum cell size • However, the resulting coherence length is still larger than typical WLAN cell sizes Andreas Wolf, Dr. Wolf & Associates

  11. Backup • Simulation results PSSS31 EbN0 versus Pb Simulation over 1 E+06 bits Andreas Wolf, Dr. Wolf & Associates

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