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This paper discusses a method for minimizing buffer placements while routing non-critical nets to improve slew rate and reliability in integrated circuits, enhancing overall performance and reducing power consumption. The approach optimizes buffer insertion to enhance signal quality and ensure timing constraints are met. Through careful planning, designers can achieve better control over signal integrity and robustness.
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Minimum-Buffered Routing of Non-Critical Nets for Slew Rate and Reliability Control B. Liu, A.B. Kahng, I. Mandoiu