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f.p.e.l

Field Programmable Embedded Logic. f.p.e.l. Goals. Understand the F.P.E.L Overview of how to develop software and program the system. What is A F.P.E.L. A FPEL is an embedded system which is programmable at the software level and configurable at the hardware level. Contents of a F.P.E.L.

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f.p.e.l

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  1. Field Programmable Embedded Logic f.p.e.l

  2. Goals • Understand the F.P.E.L • Overview of how to develop software and program the system

  3. What is A F.P.E.L • A FPEL is an embedded system which is programmable at the software level and configurable at the hardware level.

  4. Contents of a F.P.E.L • A FPEL consists of the following components. • An FPGA ( Field Programmable Gate Array ) • Microprocessor • Nonvolatile Memory ( flash ) • Volatile memory ( DDR, SRAM, etc ) • Custom circuitry, ASICs

  5. The F.P.E.L Hardware • The hardware on my FPEL contains the following components. • Xilinx FPGA ( Spartan 3 ) • PIB ( Peripheral Interconnect Bus ) • Quik Silva ( 32 bit Custom Microprocessor ) • I2C Bus Master • SPI Bus Master • UART • SRAM Controller • Pulse Width Modulation Encoders • Pulse Width Modulators • 7 Segment Display Controller • More to come..

  6. Hardware continued …

  7. A little about Quik Silva • Custom 32 bit Microprocessor • RISK Architecture based • 5 Stage Pipeline • Pipelined Microprogrammed Sequencer • Configurable Architecture • Currently using the MIPs Architecture and compiler.

  8. Software Platform • The software processing environment is currently Cygwin. • Why Cygwin ? • GCC compilers • Mips compiler • SDE-Lite ( Mips compiler and tools set )

  9. Example Code • Sensor Calibration Routine • Sensor_calibration_routine.cpp • global.h

  10. Software Programming Process • sde-as -mips1 startup.s -o startup.o • sde-g++ -c -g -mtune=r3k -mips1 sensor_calibration_routine.cpp -o snr_chk.o • sde-ld -mips1 -T ph.ld startup.o snr_chk.o -o snr_chk.bin • sde-objdump --disassemble --line-numbers --source snr_chk.bin > disassembly.list • zcv snr_chk.bin code.bin data.bin > compile.log • disassembly.list • compile.log • Program_code.coe

  11. Xilinx Tools • Now that we have the program code we need to download it into either the onboard flash or the internal SRAM. • How do we do that? • Xilinx ISE Tool Suite. • Invoke CoreGen • Update coe files • Run synthesis, mapping, place and route • Generate bit file

  12. Run Impact or other software

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