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This presentation by Jie Li from Stevens Institute of Technology explores the current work and advancements in VHDL Function CLBM, focusing on the inference of VHDL components from XML representations. It covers structural elements such as entity, architecture, component declaration, and instantiation, while proposing a solution to represent actual and formal signals in paths using two input/output places. Additionally, future work will address parallel and sequential structures, timing issues related to clocks, and the inclusion of more VHDL elements.
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VHDL function CLBM and Inference Presenter: Jie Li Stevens Institute of Technology Sep 2, 2010
Outline • Current work and Progress • VHDL Function CLBM based on the rules • Inference of VHDL components from XML representations • Future work
Signals in Path • Solution: For each a path, use two input/output places to describe the actuals and formals, respectively.
Future work • Parallel and sequential structure • Timing issue (clock) • More VHDL elements