Future Low Power Superconductor Logic

1. Future Low Power Superconductor Logic Adam Sarhage

2. Introduction • Current CMOS technology is reaching its theoretical limits for operating speed, and the next generation of supercomputers could require hundreds of megawatts of power to operate if based on CMOS technology. • Superconducting logic, which uses zero-resistance superconductors, could provide the basis for future supercomputers using 1/300th of the power required by a comparable CMOS supercomputer.

3. Josephson Junctions • Comprised of a non-superconducting material or insulating material sandwiched between two superconducting materials • Superconducting electronics are able to pass though without resistance until the critical current is reached Superconducting Material Insulating Material Schematic Symbol I-V Curve

4. Josephson Transmission Line (JTL) • Using the properties of the Josephson junction, circuits can be built which pass individual flux quanta (a quantum being the smallest amount of magnetic flux) through an IC.

5. Ways of Biasing the JTL • Traditionally, as is the case with Rapid Single Flux Quantum (RSFQ) technology, the transmission lines are biased using DC current. • This DC current requires a resistor dissipating power at each point set of Josephson Junctions on the JTL. • As the technology scales up, a substantial and prohibitive amount of power is dissipated in the DC biasing resistors.

6. Ways of Biasing the JTL • A new technology, Reciprocal Quantum Logic (RQL) seeks to eliminate the DC biasing resistors by providing the biasing current through a transformer coupled AC bias/clock line.

7. Properties of RQL • Logical bits are stored in the phase of the flux quanta. • A logical “1” is a produced by a flux quantum’s phase shift of +2π during the positive half of the clock cycle followed by a phase shift of -2π during the immediately proceeding negative half of the clock cycle. • A logical “0” is produced by not changing the phase of a flux quantum during the clock cycle.

8. Challenges facing RQL • RQL requires a JTL buffer between the output of a logic gate and the input of another logic gate. • A finite number of logic gates and buffers can be placed on a single phase of the clock. • With a 20GHz clock, approximately 4 gates/buffers can be on the same clock phase.

9. Challenges facing RQL • Gates/buffers can only be connected to their own clock phase or the next highest clock phase. (e.g. A phase 00 buffer can only be connected to a phase 00 or phase 01 buffer, not a phase 10 or 11 buffer.) • This makes synthesis using VHDL unique and challenging.

10. Sources • Fulton, T. A., R. C. Dynes, and P. W. Anderson. "The Flux Shuttle-A Josephson Junction Shift Register Employing Single Flux Quanta." Proceedings of the IEEE 61.1 (1973): 28-35. Print. • Herr, Quentin P., Anna Y. Herr, Oliver T. Oberg, and Alexander G. Ioannidis. "Ultra-low-power Superconductor Logic." Journal of Applied Physics (2011) • Oberg, Oliver T. "SUPERCONDUCTING LOGIC CIRCUITS OPERATING WITH RECIPROCAL MAGNETIC FLUX QUANTA." Diss. University of Maryland, College Park, 2011. Web. <http://drum.lib.umd.edu/bitstream/1903/12338/1/Oberg_umd_0117E_12789.pdf>.

11. Questions?