MPC850

1. MPC850

2. Reference Manuals • MPC850 Family User Manual • PowerPC Programming Environment Manual • Course Home Page http://calab.kaist.ac.kr/~maeng/cs310/micro02.htm • Motorola Home Page http://e-www.motorola.com

3. Overview • Versatile, one-chip, integrated communication processor • Embedded PowerPC core • Versatile memory controller • Communication processor module (CPM) • Serial communication controllers (SCCs) • One USB • Etc.

5. Embedded PowerPC core • Single issue, 32-bit version • Branch folding and prediction • 2-K byte I-cache, 1K byte D-cache • 2-way set-associative • Physical • MMUs with 8-entry TLBs • 4K, 16K, 256K, 512K, and 8MB page sizes

6. Other Features • Dynamic data bus sizing : 8-, 16-, 32-bit • CPU clock : 0-80MHz • System Integration Unit (SIU) • Memory Controller • General Purpose timer • CPM, SCCs, SMCs, etc.

7. PowerPC Architecture

8. PowerPC instruction set • Overview • Operand Conventions • PowerPC Registers and programming model • Addressing Modes • Instruction Set • Cache model • Exception Model • Memory management model

9. PowerPC Architecture • Motorola, IBM, Apple computer • Power Architecture: RS/6000 family • 64-bit architecture with a 32-bit subset • Three Levels of the architecture • Flexibility – degrees of SW compatibility • UISA (User instruction set architecture) • VEA (Virtual environment architecture) • OEA (Operating environment architecture)

10. Features not defined by the PowerPC Architecture • For flexibility • System bus interface signals • Cache design • The number and the nature of execution units • Other internal micro-architecture issues

11. Endianness • Relationship between bit and byte/word ordering defines endianness: bit 31 bit 0 bit 0 bit 31 byte 3 byte 2 byte 1 byte 0 byte 0 byte 1 byte 2 byte 3 little-endian big-endian ARM, Intel PowerPC, IBM, Motorola

12. Programming Model – Registers

14. PowerPC programming model - Register Set • User Model – UISA (32-bit architecture) Condition register GPR0(32) FGPR0(64) CR(32) GPR1(32) FGPR1(64) FP status and control register GPR31(32) FPSCR(32) FGPR31(64) Count register XER register Link register XER(32) LR(64/32) CTR(64/32)

15. Condition Registers (CR) • For testing and branching CR0 CR1 CR2 CR3 CR4 CR5 CR6 CR7 0 31 FP Condition register CRn Field – Compare Instruction For all integer instrs. Bit0: Negative(LT) Bit1: Positive(GT) Bit2: Zero (EQ) Bit3: Summary Overflow(SO) back

16. XER Register (XER) back

17. XER Register (XER), cont’d

18. Link Register (LR), Count Register (CTR) bclrx (bc to link register) Branch with link update

19. Counter Register • Loop count

20. VEA Register Set – Time Base

21. OEA Register Set

22. Machine State Register (MSR)

25. Addressing Modes • Effective Address Calculation • Register indirect with immediate index mode • Register indirect with index mode • Register indirect mode

26. Register Indirect with Immediate Index Addressing back

27. Register Indirect with Index back

28. Register Indirect back

29. Instruction Formats • 4 bytes long and word-aligned • Bits 0-5 always specify the primary opcode • Extended opcode

30. Instruction set • Integer • Floating-point • Load and store • Flow control • Processor control • Memory synchronization • Memory control • External control

31. Summary • UISA, VEA, OEA • Register set • Fixed size instruction - RISC • Load and store architecture • 3 addressing modes • Condition Register Update – Rc field • 8 condition registers • Branch addressing modes • BO, BI fields • Relative, absolute, LR, CTR