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Learn about hardware interrupts in computer systems, including how the Programmable Interrupt Controller (PIC) handles them, the role of Interrupt Request Registers, and the process of interrupt handling. Discover how interrupts are managed and prioritized, and explore the cascading setup of PICs for efficient processing of interrupts.
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Interrupts CS318 Project #3
Credits Google http://www.beyondlogic.org/interrupts/interupt.htm
On a Interrupt Request • Processor finishes current instruction • Pushes stuff on stack • Think of only EFLAGS and EIP for now • Invokes appropriate Interrupt Service Routine • iret – pops stuff off of stack
How many Interrupts ? • 256 total • Most of them software interrupts • 15 hardware interrupts • The Programmable Interrupt Controller (PIC) handles hardware interrupts
Hardware Interrupts • Two 8259 PIC IC chips • Base addresses 0x20h and 0xA0h
Control logic IRQ 0 is asserted
Interrupt Mask Register (IMR) Control logic Check if IRQ is masked
Interrupt Request Register (IRR) Interrupt Mask Register (IMR) Control logic Hold in IRR until processed
Interrupt Request Register (IRR) Interrupt Mask Register (IMR) Priority Resolver Control logic Send INT to processor
After finishing current instruction, checks if interrupts disabled in EFLAGS
Interrupt Request Register (IRR) Interrupt Mask Register (IMR) Priority Resolver Control logic Processor replies with INTA
In Service Register (ISR) Interrupt Request Register (IRR) Interrupt Mask Register (IMR) Priority Resolver Control logic Store in ISR, reset bit in IRR
In Service Register (ISR) Interrupt Request Register (IRR) Interrupt Mask Register (IMR) Priority Resolver Control logic Processor asks for data
In Service Register (ISR) Interrupt Request Register (IRR) Interrupt Mask Register (IMR) Priority Resolver Control logic PIC supplies data
In Service Register (ISR) Interrupt Request Register (IRR) Interrupt Mask Register (IMR) Priority Resolver Control logic Processor sends EOI
In Service Register (ISR) Interrupt Request Register (IRR) Interrupt Mask Register (IMR) Priority Resolver Control logic PIC resets ISR
Small matter of cascading PICs • 2nd PIC at 0xA0 was a later addition • Setup in master-slave configuration to preserve compatibility • You don’t need to worry about it
The End Questions?