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Understanding Hardware Interrupts in Computer Systems

Learn about hardware interrupts in computer systems, including how the Programmable Interrupt Controller (PIC) handles them, the role of Interrupt Request Registers, and the process of interrupt handling. Discover how interrupts are managed and prioritized, and explore the cascading setup of PICs for efficient processing of interrupts.

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Understanding Hardware Interrupts in Computer Systems

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  1. Interrupts CS318 Project #3

  2. Credits Google http://www.beyondlogic.org/interrupts/interupt.htm

  3. On a Interrupt Request • Processor finishes current instruction • Pushes stuff on stack • Think of only EFLAGS and EIP for now • Invokes appropriate Interrupt Service Routine • iret – pops stuff off of stack

  4. How many Interrupts ? • 256 total • Most of them software interrupts • 15 hardware interrupts • The Programmable Interrupt Controller (PIC) handles hardware interrupts

  5. Hardware Interrupts • Two 8259 PIC IC chips • Base addresses 0x20h and 0xA0h

  6. PIC

  7. Control logic IRQ 0 is asserted

  8. Interrupt Mask Register (IMR) Control logic Check if IRQ is masked

  9. Interrupt Request Register (IRR) Interrupt Mask Register (IMR) Control logic Hold in IRR until processed

  10. Interrupt Request Register (IRR) Interrupt Mask Register (IMR) Priority Resolver Control logic Send INT to processor

  11. After finishing current instruction, checks if interrupts disabled in EFLAGS

  12. Interrupt Request Register (IRR) Interrupt Mask Register (IMR) Priority Resolver Control logic Processor replies with INTA

  13. In Service Register (ISR) Interrupt Request Register (IRR) Interrupt Mask Register (IMR) Priority Resolver Control logic Store in ISR, reset bit in IRR

  14. In Service Register (ISR) Interrupt Request Register (IRR) Interrupt Mask Register (IMR) Priority Resolver Control logic Processor asks for data

  15. In Service Register (ISR) Interrupt Request Register (IRR) Interrupt Mask Register (IMR) Priority Resolver Control logic PIC supplies data

  16. In Service Register (ISR) Interrupt Request Register (IRR) Interrupt Mask Register (IMR) Priority Resolver Control logic Processor sends EOI

  17. In Service Register (ISR) Interrupt Request Register (IRR) Interrupt Mask Register (IMR) Priority Resolver Control logic PIC resets ISR

  18. Small matter of cascading PICs • 2nd PIC at 0xA0 was a later addition • Setup in master-slave configuration to preserve compatibility • You don’t need to worry about it

  19. IRQ 2 routed via IRQ9

  20. INT of PIC2 via IRQ2

  21. All interrupts from PIC2 routed via PIC1 to processor

  22. EOI for interrupts from PIC2 must be sent to both PICs

  23. The End Questions?

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