Performed by: Omer Zimerman Roi Ben-Haim Instructor: Guy Revach

1. Technion - Israel institute of technology department of Electrical Engineering הטכניון - מכון טכנולוגי לישראלהפקולטה להנדסת חשמל High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות דו”ח סיכום פרויקט (סופי) Subject Digit recognition hardware implementation Performed by: Omer Zimerman Roi Ben-Haim Instructor: Guy Revach סמסטר חורף 2013/2014 1

2. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Abstract Neural Network is a Machine Learning System designed for supervised learning using examples. Such network can be used for handwritten digit recognition, and when used in software is in-efficient in both time and resources. This project is the third part of a 3-parts project. Our goal is to implement an efficient hardware solution to the handwritten digit recognition problem. Implementing dedicated HW to this task is part of a new trend in VLSI architecture called heterogeneous computing- design of a system on chip with many accelerators for different tasks, which will achieve better performance/power ratio, each for its purposed task. 2

3. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות System description The system comprises of ML-605 evaluation board, including Xilinx’s Virtex 6 FPGA, connected to a PC via UART interface. A matlab GUI was created, enabling the user to easily send an input image (which is a single digit in the range 0-9, of size 29x29 pixels) to the FPGA via the UART i/f. The recognition process than takes place on dedicated circuitry in the FPGA. After the recognition process is finished, the results are sent back to the PC (via UART), where they are presented to the user in a clear form through the matlab application. 3

4. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות Specification • Hardware • VirtexML-605 evaluation board, including Virtex 6 FPGA • Software • Matlab GUI for interacting with the FPGA using UART I/F 4

5. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות System Block Diagram PC ML-605 board Matlab application Virtex 6 FPGA UART i/f 5

6. High speed digital systems laboratory המעבדה למערכות ספרתיות מהירות FPGA Block Diagram 6