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Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric Networks-on-Chip

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Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric Networks-on-Chip

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    1. Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric Networks-on-Chip Donghyun Kim, Kwanho Kim, Joo-Young Kim, Seungjin Lee and Hoi-Jun Yoo Dept. of EECS Korea Advanced Institute of Science and Technology (KAIST)

    2. 2 Outline Introduction Circuit Techniques for efficient NoC Implementation Memory-Centric NoC Architecture NoC operation Performance Evaluation & Implementation Results Conclusions

    3. 3 Our direction of NoC implementation Introduction

    4. 4 Hierarchical Star Topology (1/2) NoC topologies in Real Chips

    5. Hierarchical Star Topology (2/2) Energy & Area comparison

    6. From the Circuit Designer’s Viewpoint Keep it SIMPLE and make the Chip WORK! Chip aware protocol: HW Complexity On-chip serialization: Small Area Synchronization: Clock Complexity Low voltage swing link: Low Power Crossbar switch partial activation: Low Power Techniques for efficient NoC

    7. Packet Format and Protocol Aligned packet format reduces hardware complexity

    8. 8 On-chip Serialization (1/2) Concept and effects of On-chip Serialization

    9. On-chip Serialization (2/2) High speed SERDES (WAFT)

    10. Synchronization Source synchronous - matched delay synchronizer

    11. Low voltage signaling Scheme and transceiver circuits

    12. Crossbar Partial Activation Crossbar partial activation reduces unneeded power dissipation

    13. Memory-Centric NoC

    14. Memory Centric NoC – Architecture (1/2) Overall Architecture 10 RISC processors 8 dual port memories 4 Channel controllers Hierarchical-star topology packet switching network Mesochronous comm.

    15. Memory Centric NoC – Architecture (2/2) Architectural features

    16. Memory Centric NoC – Operation (1/2) Overview of the MC-NoC operation

    17. Memory Centric NoC – Operation (2/2) Valid check logic manages data coherency

    18. Memory Centric NoC - Application Target application SIFT based object recognition

    19. Memory Centric NoC – Advantages (1/3) Task mapping on conventional mesh NoC

    20. Memory Centric NoC – Advantages (2/3) Task mapping on the proposed MC-NoC

    21. Memory Centric NoC – Advantages (3/3) Flexibility of task mapping

    22. Memory Centric NoC – Performance Report Average latency & power breakdown

    23. Implementation Results Chip photograph & specification

    24. Conclusion Real Chip implementation issues Simple architecture and circuits Chip performance > Network performance Memory Centric NoC Hybrid of Shared Memory and Star topology Low overhead communication Concurrent inter-processor communications MC-NoC for object recognition processor 0.18um CMOS process 7.7mm x 5mm, 1.4W at 1.8V and 81.6GOPS

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