HW/SW Interface

1. HW/SW Interface Operating Systems Design and Implementation

2. Foreground/Background Systems • Often referred to as super-loops Infinite loop calling modules ISR Handle Asynchronous Events ISR ISR Interruption occurred Foreground (interrupt level) Background (task level)

3. Interrupt Service Routines • Handle critical operations • can take longer than they should • make data available for background routines • processing of such information is referred to task-level response

4. Example: EFI System(Electronic Fuel Injection) • What are the components? Throttle Body Cold start solenoid Air-flow meter Injectors O2 sensor ECU Water temperature sensor Distributor sensors High pressure fuel pump manifold sensor

5. EFI System • How does it work? • fundamentally, it manages three necessities to start and maintain operation of a gasoline engine • fuel • spark • air

6. EFI System • What happen to the EFI system when you start a car? • What happen to the EFI system when you drive a car?

7. Dissecting EFI System • Tasks • ISRs

8. EFI System • Critical section (atomic or indivisible) • any possible critical regions in our tasks? • Mutual exclusion? • Reentrant code? • functions can be used by multiple tasks without causing data corruption • Priority inversion problem?

9. Priority Inversion • Assume task 3 has lower priority than task 1. • Task 1 is doing I/O so Task 3 gets to run • Task 3 is in the middle of accessing a shared resource (obtain semaphore) • Task 1 finishes so it preempts Task 3 • Task 1 wants to access the same resource but can’t since Task 3 has the semaphore

10. Priority Inversion • In this scenario, the priority of Task 1 is reduced to that of Task 3. • What is a good solution? Priority Inheritance

11. Priority Inversion • Priority Inheritance • Task 1 is doing I/O so Task 3 gets to run • Task 3 is in the middle of accessing a shared resource (obtain semaphore) • Task 1 finishes so it preempts Task 3 • Task 1 wants to access the same resource but can’t since Task 3 has the semaphore; thus the kernel raises the priority of Task 3 to the same as Task 1 • Task 3 gets to finish and releases the resource. The priority is reset to the original value • Task 1 is selected if it still has the highest priority

12. Assigning Task Priority • Rate monotonic scheduling • tasks with the highest rate of execution are given the highest priority • Assume all tasks are periodic • Tasks do not synchronize with another, share resources, and exchange data • Preemptive scheduling is used

13. Assigning Task Priority

14. Providing Mutual Exclusion • Disabling interrupt • Test and Set operation • hardware support (TSL operation) • Disabling scheduler • Semaphores • how is semaphore implemented?

15. Disabling Interrupt • X86 • CLI (disable interrupt) • STI (enable interrupt)

16. Busy Waiting

17. Busy Waiting

18. Semaphore • Is a type that has a counter and a delay queue • require OS support as processes in the delay queue are blocked • implementation often requires other primitive support (disabling interrupt, etc.)

19. Semaphore assumes the existence of binary semaphore operations upb and downb implemented with a test-and-set instruction and busy waiting

20. Intertask Communication • Message mailbox • Message queues • often use to process interrupt

21. Interrupts • A hardware mechanism used to notify the CPU that asynchronous events have occurred • Upon completion, the programs return to: • background for a foreground/background system • the interrupted task for non-premptive kernel • the higest priority task ready to run for premptive kernel

22. Example: Interrupt in NIOS IE bit to enabling interrupt IPRI bits for priority MISC bits for interrupt control

23. Source of Exceptions (NIOS) • External Hardware interrupt Sources • External logic for producing the 6-bits interruptnumber & asserting the IRQ input pin is automatically generated by the SOPC builder and is included in the Peripheral Bus Module (PBM). • Internal Exception Sources • 2 sources of internal exceptions • Register window-overflow, Register window-underflow • Direct Software Exceptions • Software can request that control be transferred to an exception handler by issuing a TRAP instruction.

24. External Hardware Interrupts • Active-high interrupt signal: irq • Level sensitive • Sampled synchronously at the rising edge of Nios clock • Should stay asserted until the interrupt is acknowledged by software • 6-bit Input Interrupt Number: irq_number[5:0] • Identifies the highest priority interrupt currently requested • Highest priority = 0 (irq #0 to #15 are reserved) • Lowest priority = 63

25. External Hardware Interrupts • Nios will process the indicated exception if • IE= 1 – i.e. external interrupts & internal exceptions are enabled, AND • The interrupt number is smaller (lower or equal) than the IPRI field value

26. Internal Hardware Interrupts

27. Interrupt Service Routine Handler nr_installuserisr( int trapNumber, void *ISRProcedure, int context) trapNumber is the exception number to be associated with a service routine ISRProcedure is a routine which has a prototype oftypedef void (*Nios_isrhandlerproc) (int context); context is a value that will be passed to the routine specified by isrProcedure

28. ISR Handler • This routine installs an interrupt service routine for a specific exception number • If nr_installuserisr() is used to set up the exception handler, then the exception handler can be an ordinary C routine

29. ISR Process Memory Main Program Save Context • Interrupt occurs • Current state is saved (Context) • ISR address is retrieved from the vector table based on the interrupt number • Jump to ISR routine Runs to completion • Context is restored • Program resumes Restore Context ISR Vector Table

30. ROM instruction @irq_subroutine 0 … @clock_adj_ISR @RealTime_ISR … @irq_subroutine 63 Vector Table 0xFFFF … 0xFF0F 0xFF0E … 0xFFC0 stack RAM ISR Implementation Specify your # IRQ Declare your IRQ subroutines Update the ISR vector table Write your IRQ Subroutine Write your IRQ Subroutine

31. Interrupt Example • UART (Universal Asynchronous Receiver Transmitter) • Transferring data between processor and I/O devices • Handle one 8-bit data at a time • Transfer in parallel between UART and Processor and in bit-serial between I/O device and UART

32. JTAG UART Used to provide a connection between a Nios II processor and the host computer connected to the DE 2 board

33. JTAG UART • Data and control registers accessed by Nios II as memory locations # of char remaining in the read FIFO read/write data from FIFOs read valid read/write interrupt enable available space in write FIFO read/write/JTAG pending

34. JTAG UART

35. JTAG UART • Polling vs. Interrupt