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LOGIC DESIGN

LOGIC DESIGN. L ARGE S CALE I NTEGRATED CIRCUITS, LSI ( BÜYÜK ÖLÇEKLİ LOJİK DEVRE ELEMANLARI). EE33201 COURSE ASSESMENT MATRIX. SYMBOLS. PROGRAMABLE LOGIC DEVICES (PLD) (PROGRAMLANBİLİR LOJİK DEVRELER). PROM. PAL. PLA.

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LOGIC DESIGN

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  1. LOGIC DESIGN LARGE SCALE INTEGRATED CIRCUITS, LSI (BÜYÜK ÖLÇEKLİ LOJİK DEVRE ELEMANLARI) Ertuğrul Eriş

  2. EE33201 COURSE ASSESMENT MATRIX

  3. SYMBOLS Ertuğrul Eriş

  4. PROGRAMABLE LOGIC DEVICES (PLD) (PROGRAMLANBİLİR LOJİK DEVRELER) PROM PAL PLA PLD: Programmable Logic Devices: Combinational, Sequentials PROM: Programmable Read Only Memory PAL: Programmable Array Logic PLA: Programmable Logic Array Ertuğrul Eriş

  5. 1024 X 16-MEMORY (BELLEK) Finite memory versus combinational circuit. Ertuğrul Eriş

  6. ROM BLOCK DIAGRAM ROM: Read Only Memory k: number of address bits 2k: number of addresses 2k x n = number of connections between AND and OR gates -switch(anahtar, fuse(sigorta)- Ertuğrul Eriş

  7. 32 X 8 ROM ANDs fixed ORs programable k: address bits= 5 2k: number of addresses, n-bit words= 32, n = 8 2k x n = 32 x 8 = 256 connections Ertuğrul Eriş

  8. ROM PROGRAMMING VE dizisi sabit VEYA dizisi programlanabilir ROM memory(bellek), is it combinational? Ertuğrul Eriş

  9. ROM APPLICATION: SQUARE VE fixed VEYA programable Ertuğrul Eriş

  10. TECHNOLOGICAL CHANGES • PROM • Programmable Read Only Memory • EPROM • Eraseable Programmable Read Only Memory • EEPROM • Electronically Eraseable Programmable Read Only Memory Ertuğrul Eriş

  11. PAL • common commercial • 4 input/4 output • 4 sections: • 3 AND-1 OR AND programable OR fixed In designing with PAL, The Boolean functions must be Simplified to fit into each section Ertuğrul Eriş

  12. PAL EXAMPLE w(A, B, C, D) = Σ (2,12,13) x(A, B, C, D) = Σ (7,8,9,10,11,12,13,14,15) y(A, B, C, D) = Σ (0,2,3,4,5,6,7,8,10,11,15) z(A, B, C, D) = Σ (1,2,8,12,13) w = ABC’ + A’B’CD’ x = A + BCD y = A’B + CD + B’D’ z = ABC’ + A’B’CD’ +AC’D’ + A’B’C’D = w + AC’D’ + A’B’C’D Ertuğrul Eriş

  13. PLA • n inputs, k product terms, m outputs • n buffer-inventor gates, k AND gates, m OR gates, m XOR gates • 2n x k connections between and AND array gates • k x m connections between AND and OR gates • m connections with the XOR gates • Typical: n = 16, k = 48, m = 8 • Programming: Mask programmable PLA, Field programmable PLA AND array programable OR array programable Ertuğrul Eriş

  14. THREE INPUTS/TWO OUTPUTS4 AND -2 OR GATE PLA AND array programable OR array programable Use of the EX-OR gate at the outputs?. Ertuğrul Eriş

  15. PLA EXAMPLE AND array programable OR array programable F1(A, B, C) = Σ (0, 1, 2, 4) F2(A, B, C) = Σ (0, 5, 6, 7) F1 = (AB + AC+ BC)’ F2 = AB + AC+ A’B’C’ Ertuğrul Eriş

  16. PROGRAM DESIGN DEPT, PROGRAM G R A D U A T E S T U D E N T STUDENT P R OG R A M O U T C O M E S PROGRAM OUTCOMES P R OG R A M O U T C O M E S STATE, ENTREPRENEUR FIELD QALIFICATIONS EU/NATIONAL QUALIFICATIONS KNOWLEDGE SKILLS COMPETENCES NEWCOMERSTUDENT ORIENTIATION GOVERNANCE Std. questionnaire ALUMNI, PARENTS ORIENTIATION STUDENT PROFILE Std. questionnaire FACULTY NGO STUDENT, ??? CIRCICULUM ??? INTRERNAL CONSTITUENT Std. questionnaire EXTRERNAL CONSTITUENT EXTRERNAL CONSTITUENT REQUIREMENTS EU/NATIONAL FIELD QUALIFICATIONS PROGRAM OUTCOMES QUESTIONNAIRES QUALITY IMP. TOOLS GOAL: NATIONAL/INTERNATIONAL ACCREDITION

  17. BLOOM’S TAXONOMYANDERSON AND KRATHWOHL (2001) !!Listening !! Doesn’t exits in the original!!! http://www.learningandteaching.info/learning/bloomtax.htm Ertuğrul Eriş

  18. ULUSAL LİSANS YETERLİLİKLER ÇERÇEVESİ BLOOMS TAXONOMY Ertuğrul Eriş

  19. COURSE ASSESMENT MATRIX LEARNING OUTCOMES Ertuğrul Eriş

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