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fADC125V2 Production and Testing Status Update - June 2013

This report provides an update on the production and testing status of the fADC125V2, a 125 MSPS pipelined flash ADC. As of June 3rd, 2013, 175 out of 217 units have been received, with 45 delivered as of May 31st. The production is currently facing issues, particularly with a ~30% failure rate in first articles due to mixed boards. A contractor has been hired to aid quality assurance, reducing the failure rate to ~13%. Ongoing testing includes single board tests and full crate testing along with firmware development for improved features and integration.

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fADC125V2 Production and Testing Status Update - June 2013

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  1. fADC125 Status Cody Dickover • Procurement • Testing • Firmware • Future work Hall D Collaboration June 3rd, 2013

  2. fADC125V2 – 125 MSPS Pipelined Flash ADC (Gerard V, Cody D, FJB) Production Status • Currently in Production • 175 out of 217 received (~80%) • 45 delivered Friday 5/31/2013 • Working with QA on manufacturing issues • Final delivery due 6/14/2013

  3. fADC125V2 – 125 MSPS Pipelined Flash ADC (Gerard V, Cody D, FJB) Production Issues • First articles • 40 first articles • ~30% failure rate • Main issues related to “mixed” board • Full Production • MTEQ hired contractor to aid QA • Down to ~13% failure rate (~70 units) • Weekly conference calls

  4. fADC125V2 – 125 MSPS Pipelined Flash ADC (Gerard V, Cody D, FJB) • Testing Status • 118 units tested (~54%) • Working RMA’s with MTEQ QA • Single board tests ongoing • Full crate testing begun • Temperature probe • Noise histogram • Thanks to Ed J.

  5. fADC125V2 – 125 MSPS Pipelined Flash ADC (Gerard V, Cody D, FJB) • Some temperature data • Fan speed 3000 RPM • Temp Celcius • Probe location ADCs

  6. fADC125V2 – 125 MSPS Pipelined Flash ADC (Gerard V, Cody D, FJB) • Noise Histogram • Sample of 2000 point waveform capture • 12 bit • Open input, midscale offset • RMS for these 3 CH: 0.47, 0.46, 0.51 • Prototype RMS ~0.52

  7. fADC125V2 – 125 MSPS Pipelined Flash ADC (Gerard V, Cody D, FJB) Firmware development • Testing_v1 currently in trial w/new interface • Integrated some new features from test bed • Clock select, trigger select, unique ID • 3 boards sent to Naomi J. at CMU for work on front end algorithms • New “official release” still in progress • New driver, thanks to Bryan Moffit

  8. Future work • Continue firmware integration, update register maps • Continue full crate testing, low level DC check • Data formatting • Develop infrastructure and eventually algorithms (in collab with CDC/FDC groups) for onboard signal processing

  9. Questions / Comments?

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