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IEEE Std. P1687.1 Translator and Protocol

IEEE Std. P1687.1 explores the use of functional ports such as SPI and I2C to access IEEE Std. 1687 networks, aiming to minimize transported data and hardware area. The protocol and hardware developed enable efficient communication and experimentation on FPGA with UART as the functional port. The focus is on accessing embedded instruments for activities like power management, clock control, chip configuration, memory and scan tests, etc. The protocol involves control and data commands to interact with the instruments, ensuring effective communication within the IEEE Std. 1687 framework.

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IEEE Std. P1687.1 Translator and Protocol

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  1. IEEE Std. P1687.1: Translator and Protocol Erik Larsson, Prathamesh Murali, and Gani Kumisbek

  2. Purpose • Context: IEEE Std. P1687.1 explore functional ports (SPI, I2C and so on) instead of the test port of IEEE Std. 1149.1 to access IEEE Std. 1687 networks • Developed: protocol and hardware to access IEEE Std. 1687 • Objective: minimize transported data and area of hardware • Experiments: implementation on FPGA with UART as the functional port and compared some alternatives 2

  3. Outline • Embedded instruments and access to them • Hardware component • Protocol for communication • Experimental results • Conclusions 3

  4. Embedded instruments • Activities: power management, clock control, chip configuration, memory test, scan test, logic built-in self-test (BIST), debug/diagnosis, phase locked-loop (PLL) control, reduced pin count test, and fault insertion. • Embedded instruments: scan chains, BIST engines, cyclic redundancy check (CRC) registers, packet counters, performance monitors, analog-to-digital converters (ADCs), remapping registers, trace buffers, PLL controls, and power managers. 4

  5. Flexible and scalable access: IEEE Std. 1687 Segment Insertion Bits IEEE Std. 1687 SIB3 SIB1 SIB2 Shift-register Shift-register Shift-register i3 i1 i2 Logic 5

  6. IEEE Std. 1149.1 to access IEEE Std. 1687 IEEE Std. 1149.1 IEEE Std. 1687 SIB3 SIB1 SIB2 Shift-register Shift-register Shift-register i3 i1 i2 Logic 6

  7. IEEE Std. P1687.1 I2C/SPI/… IEEE Std. 1687 SIB3 SIB1 SIB2 Shift-register Shift-register Shift-register i3 i1 i2 Logic 7

  8. Our work Objectives Developed 1. Minimize data transported 1. Protocol UART 2. Minimize area 2. Component SIB3 SIB1 SIB2 Shift-register Shift-register Shift-register i3 i1 i2 Logic 8

  9. Simpler modelling SIB3 SIB1 SIB2 Shift-register Shift-register Shift-register i3 i1 i2 SIB3 SIB1 SIB2 i3 i1 i2 9

  10. Our work Minimize data transported Protocol UART Minimize area Component SIB3 SIB1 SIB2 i3 i1 i2 10

  11. Component PDL ICL iGetReadData SIB SIB SIB iGet i1; iWrite i3 0xFF; iApply; i1 i2 i3 UART Component SIB3 SIB1 SIB2 i3 i1 i2 11

  12. Component 1 UART Output buffer Input buffer Instrument Control Register: Operation on instruments 4 2 3 ICR SIB Control Register: SIB content FSM SCR Instrument Length Memory: Length of instruments ILM 5 SIB3 SIB1 SIB2 i3 i1 i2 12

  13. Component Set active scan-path 1 PDL iGet i1; iWrite i3 0xFF; iApply; UART ICR FSM SCR SIB1 1 SIB2 0 SIB3 1 ILM 0 1 1 SIB3 SIB1 SIB2 i3 i1 i2 13

  14. Component 2 Shift-in data PDL iGet i1; iWrite i3 0xFF; iApply; UART ICR FSM SCR SIB1 1 SIB2 0 SIB3 1 ILM a 1 SIB3 SIB1 SIB2 i3 i1 i2 14

  15. Component Data 2 Shift-in data PDL Input b3 1 b0 1 b1 1 b2 1 b4 1 b5 1 b6 1 b7 1 iGet i1; iWrite i3 0xFF; iApply; UART i1 R i2 - i3 W ICR Operation FSM SCR i1 8 i2 16 i3 8 ILM Shifts 1 SIB3 SIB1 SIB2 b i3 i1 i2 1 1 1 1 1 1 1 1 15

  16. Component 2 Shift-in data PDL iGet i1; iWrite i3 0xFF; iApply; UART ICR FSM SCR SIB1 1 SIB2 0 SIB3 1 ILM 1 0 c SIB3 SIB1 SIB2 i3 i1 i2 1 1 1 1 1 1 1 1 16

  17. Component 2 Shift-in data PDL iGet i1; iWrite i3 0xFF; iApply; UART ICR FSM SCR SIB1 1 SIB2 0 SIB3 1 ILM d 1 0 1 SIB3 SIB1 SIB2 i3 i1 i2 1 1 1 1 1 1 1 1 17

  18. Component 2 Shift-in data PDL iGet i1; iWrite i3 0xFF; iApply; UART i1 R i2 - i3 W ICR Operation FSM SCR i1 8 i2 16 i3 8 ILM FSM creates dummy data Shifts 1 0 1 SIB3 SIB1 SIB2 e i3 i1 i2 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 18

  19. Component 3 Shift-out data PDL iGet i1; iWrite i3 0xFF; iApply; UART ICR FSM SCR SIB1 1 SIB2 0 SIB3 1 ILM Discard 1 a SIB3 SIB1 SIB2 i3 i1 i2 19

  20. Component 3 Shift-out data PDL iGet i1; iWrite i3 0xFF; iApply; UART i1 R i2 - i3 W Operation ICR FSM SCR i1 8 i2 16 i3 8 SIB1 1 SIB2 0 SIB3 1 ILM Shifts Discard SIB3 SIB1 SIB2 b 1 1 1 1 1 1 1 1 i3 i1 i2 20

  21. Component 3 Shift-out data PDL iGet i1; iWrite i3 0xFF; iApply; UART ICR FSM SCR SIB1 1 SIB2 0 SIB3 1 ILM 0 Discard c SIB3 SIB1 SIB2 i3 i1 i2 21

  22. Component 3 Shift-out data PDL iGet i1; iWrite i3 0xFF; iApply; UART ICR FSM SCR SIB1 1 SIB2 0 SIB3 1 ILM 1 Discard d SIB3 SIB1 SIB2 i3 i1 i2 22

  23. Component 3 Shift-out data PDL Output b3 1 b0 1 b1 1 b2 1 b4 1 b5 1 b6 1 b7 1 iGet i1; iWrite i3 0xFF; iApply; UART i1 R i2 - i3 W ICR Operation FSM SCR i1 8 i2 16 i3 8 ILM Shifts SIB3 SIB1 SIB2 1 1 1 1 1 1 1 1 i3 i1 i2 23

  24. Our work Minimize data transported Protocol UART Minimize area Component SIB3 SIB1 SIB2 i3 i1 i2 24

  25. Protocol • Each iApply group is translated into one or more control commands followed by one or more data commands • Control commands: set values of SCR and ICR • Data commands: send “data” Control command Byte 1 b5 b4 Byte 2 b4 ICR b7 D/C b6 b3 b2 b1 b0 Address to SIB b7 b6 b5 b3 b2 b1 b0 R/W FSM SCR Data command ILM Byte 1 b4 Byte 2 b4 b7 D/C b6 b5 b3 b2 b1 b0 b7 b6 b5 b3 b2 b1 b0 Number of bytes with data that follows Fixed at design time 25

  26. Protocol: to IEEE Std. 1687 Control command Byte 1 b5 b4 Byte 2 b4 1 b7 C b6 R b3 b2 b1 b0 b7 SIB #1 b6 b5 b3 b2 b1 b0 PDL Control command 2 Byte 1 b5 b4 Byte 2 b4 iGet i1; iWrite i3 0xFF; iApply; b7 C b6 W b3 b2 b1 b0 b7 SIB #3 b6 b5 b3 b2 b1 b0 Data command 3 Byte 1 b4 Byte 2 b4 b7 D b6 b5 b3 b2 b1 b0 b7 1 b6 b5 b3 b2 b1 b0 7 bytes (56 bits) Data b3 1 b0 1 b1 1 b2 1 b4 1 b5 1 b6 1 b7 1 26

  27. Protocol: from IEEE Std. 1687 Output b3 1 PDL b0 1 b1 1 b2 1 b4 1 b5 1 b6 1 b7 1 iGet i1; iWrite i3 0xFF; iApply; UART 1 byte (8 bits) ICR FSM SCR ILM SIB3 SIB1 SIB2 i3 i1 i2 27

  28. Experiments Transported data? Protocol UART Area? Component SIB3 SIB1 SIB2 i3 i1 i2 28

  29. Experiments • Implemented on FPGA: – IEEE Std. 1687 networks with 50, 100, and 150 instruments – Schemes: Naïve, No dummy, No ILM, Proposed • Theoretical computation: Bit banging • Used BASTION PDL (write followed by read of each instrument, write to all, read from all (50 instruments give 102 iApply)) • Software to generate UART data according to protocol 29

  30. Experiments Proposed Proposed but Naïve No ILM Bit-banging no dummy data no dummy data UART UART UART UART SCR X ICR X SCR ICR SCR ICR FSM FSM FSM ILM X ILM X ILM IEEE Std. 1687 IEEE Std. 1687 IEEE Std. 1687 IEEE Std. 1687 30

  31. Experiments – data over UART 1628848 765232 222128 201110 96060 29302 1443221336 19232 14218 12832 9632 7122 6432 4832 NAIVE NAIVE NAIVE NO ILM NO ILM NO ILM NO DUMMY NO DUMMY NO DUMMY PROPOSED PROPOSED PROPOSED BIT BANGING BIT BANGING BIT BANGING NUMBER OF INSTRUMENTS: 50 NUMBER OF INSTRUMENTS: 100 NUMBER OF INSTRUMENTS: 150

  32. Experiments – data over UART CONTROL DATA DUMMY 21336 19232 6904 4832 14432 14218 12832 4832 4832 4586 3232 9632 7122 3232 3232 6432 14400 2290 4832 1632 9600 9600 9600 1632 1632 6400 6400 4800 3200 3200 PROPOSED NO ILM NO DUMMY PROPOSED NO ILM NO DUMMY PROPOSED NO ILM NO DUMMY NUMBER OF INSTRUMENTS: 50 NUMBER OF INSTRUMENTS: 100 NUMBER OF INSTRUMENTS: 150

  33. Experiments – area – configurable logic blocks 1118 742 369 147 144 140 129 123 118 103 100 96 45 45 45 IEEE STD. 1687 IEEE STD. 1687 IEEE STD. 1687 NAIVE NAIVE NAIVE NO ILM PROPOSED NO ILM PROPOSED NO ILM PROPOSED NODUMMY NODUMMY NODUMMY NETWORK NETWORK NETWORK 50 INSTRUMENTS 100 INSTRUMENTS 150 INSTRUMENTS

  34. Conclusions • We developed a hardware component and a protocol to communicate with IEEE Std. 1687 networks, demonstrated for UART • Protocol and component are general, hence applicable to other interfaces than UART • Result: Key information kept in the hardware component • An IP-provider uses our scheme for MBIST in a test chip 34

  35. IEEE Std. P1687.1: Translator and Protocol Erik Larsson, Prathamesh Murali, and Gani Kumisbek

  36. Control command Fixed: shift in content of SCR BASTION PDL 160 18000 144 15600 140 128 16000 112 120 14000 100 100 100 100 100 100 100 100 100 96 100 12000 10400 80 9600 80 10000 64 8000 60 48 6400 5200 32 6000 40 16 3200 4000 20 2000 0 1 2 3 Fixed 4 5 Proposed 6 7 8 9 0 50 100 Proposed 150 Fixed Number of instrument in an iApply group Number of instrument in IEEE Std. 1687 network

  37. SIB si 0 D Q D Q 1 SETS SETU CLR CLR tsi fso so

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