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Circuit Analysis of Synchronous Digital Systems: Setup Times and State Machines

This document serves as a comprehensive guide to analyzing synchronous digital circuits, focusing on negative and positive setup times across different scenarios. It covers the intricacies of circuit transitions, state diagrams, and output functions in systems modeled as Moore or Mealy machines. Key components like flip-flops, AND, OR, and NOT gates are examined, along with detailed timing analysis and clock rate calculations. Additionally, it presents practical examples and state transition functions, ensuring a thorough understanding of combinational and sequential circuit designs.

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Circuit Analysis of Synchronous Digital Systems: Setup Times and State Machines

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  1. מבנה המחשב - מבוא למחשבים ספרתיים Synchronous Circuits

  2. Question 10.2 - Circuit Analysis Comb. Logic AND D FF Q CLK CLK

  3. Question 10.2 - Circuit Analysis case #1 – negative setup time ti-1 ti CLK Ci D Logic Q Not stable Stable

  4. Question 10.2 - Circuit Analysis case #1 – negative setup time ti-1 ti CLK Ci D Logic Q Not stable Stable

  5. Question 10.2 - Circuit Analysis case #2 – positive setup time ti-1 ti CLK Ci Ci D Logic Q Not stable Stable

  6. Question 10.2 - Circuit Analysis case #2 – positive setup time ti-1 ti CLK Ci Ci D Logic Q Not stable Stable

  7. The Marvelous Toy

  8. Toy Design • Identifying system states • Identifying state transitions and deciding on Moore or Mealy model • Detailing the state machine transition and output functions • The combinational circuits • The Canonic circuit • Clock rate calculation

  9. Toy System States • Only the three switching elements keep state. • Each has a binary state: Left or Right • We can model the state of every switch by a single bit. • Convention: 0=Left, 1=Right • The total number of states: 23 = 8

  10. State Diagram 000

  11. State Diagram 100 0/0 000 Enter from Left Out from Left Swap X 1/0 X is Left Z is Left Y is Left 011 Enter from Right Out from Left Swap Y & Z

  12. State Diagram 100 010 0/0 1/0 0/0 000 111 1/0 011

  13. State Diagram 100 010 0/0 1/0 0/0 000 0/0 1/1 111 1/0 Enter Right Out Right Swap Y&Z 011 110 001

  14. State Diagram 100 010 0/0 1/0 0/0 000 0/0 1/1 111 1/0 0/1 1/1 011 110 001

  15. State Diagram 100 010 0/0 1/0 0/0 000 0/0 1/1 111 1/0 0/1 1/1 011 0/1 110 1/1 101 001

  16. State Diagram 100 010 0/0 1/0 0/0 000 0/0 1/1 111 1/0 0/1 1/1 011 0/1 110 1/1 1/1 101 001 0/0

  17. State Diagram 100 010 0/0 1/0 0/0 000 0/0 1/1 111 1/0 0/1 1/1 011 0/1 110 1/1 1/1 0/0 1/1 101 001 0/0

  18. State Diagram 100 010 0/0 1/0 0/0 000 0/0 1/1 111 1/0 0/1 1/1 1/1 011 0/0 0/1 110 1/1 1/1 0/0 1/1 101 001 0/0

  19. Output Function

  20. Output Function Output = YI + XZ + ZI (This is λ) • This circuit has 3 AND(2) in parallel, and then an OR(3) • No NOT gates. • Delay = D(AND)+2*D(OR) • Assuming we use OR(2) only

  21. The Next State Function of X 100 010 0/0 1/0 0/0 000 0/0 1/1 111 1/0 0/1 1/1 1/1 011 0/0 0/1 110 1/1 1/1 0/0 1/1 101 001 0/0

  22. Next State Function for X

  23. X Next State Function X = X’I’+XI (This is part of δ) • This circuit has: • 2 negations in parallel • 2 AND(2) in parallel, • and then an OR(2) • Delay = D(NOT)+D(AND)+D(OR)

  24. The Canonic Circuit Output Circuit λ Output {0,1} Input {0,1} Next State Circuit δ Next State {0,1}3 State {0,1}3 State Register

  25. Stripping away the Flip-Flops Output {0,1} Output Circuit λ Input {0,1} Next State Circuit δ Next State {0,1}3 State {0,1}3 Q-port D-port

  26. Attaching Delay Output {0,1} Output Circuit pd(λ) setup(OUT) Input {0,1} pd(IN) Next State Circuit pd(δ) Next State {0,1}3 State {0,1}3 tpd tsu Q-port D-port

  27. Finding the Clock Rate Output {0,1} Output Circuit pd(λ) setup(OUT) Input {0,1} pd(IN) Next State Circuit pd(δ) Next State {0,1}3 State {0,1}3 tpd tsu Q-port D-port

  28. The Clock Rate We are done!

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