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This paper presents a novel approach to addressing the limitations of traditional shared buses in data communication among multiple IPs in embedded systems. By implementing a crossbar on-chip bus architecture, the designed platform allows multiple masters to communicate simultaneously with several slaves, thereby eliminating bottlenecks typically encountered in conventional systems. Experimental results demonstrate significant improvements in data throughput and efficiency. This design aims to optimize the performance of multimedia SoC platforms, enhancing capabilities for modern applications.
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Design of Multimedia SoC Platform with a Crossbar On-chip Busfor Embedded SystemsHongkyun Jung, Xianzhe Jin, Younjin Jung, Ok Kim, Byoungyup Lee,Jungbum Heo and Kwangki RyooGraduate School of Information and Communication, Hanbat National University,{hkjung, kkryoo}@hanbat.ac.kr Reporter :LYWang 2013.9.11
Introduction • What’s the problem: • Data communication of multiple IPs is limited by the bottleneck on traditional shared bus. • When a master communicate with one slave , the other master can not communicate with other free slave. • Proposed method: • Crossbar on-chip bus • Multiple channel that allow more than one master to use the bus.
