PI: Prof. Jason Cong (UCLA) Graduate Students: Chin-Chih Chang, David Pan, Xin Yuan

Interconnect Planning, Synthesis, and Layout for Performance, Signal Reliability and Cost OptimizationSRC Task ID: 605.001 PI: Prof. Jason Cong (UCLA) Graduate Students: Chin-Chih Chang, David Pan, Xin Yuan Industrial Liaisons: Dr. Prakash Arunachalam (Intel) Dr. Norman Chang (HP) Dr. Wilm Donath (IBM) Dr. Stefan Rusu (Intel) SRC Monitor: Lawrence Arledge (SRC)

Objective: investigate an interconnect-centric design flow and methodology, consisting of: Interconnect Planning Interconnect Synthesis Interconnect Layout Project Overview

Interconnect Performance Estimation Models (IPEM) • OWS, SDWS, BISWS Interconnect Optimization (TRIO) • Topology Optimization with Buffer Insertion • Wire sizing and spacing • Simultaneous Buffer Insertion and Wire Sizing • Simultaneous Topology Construction • with Buffer Insertion and Wire Sizing Interconnect Layout Route Planning Point-to-Point Gridless Routing Overview of Interconnect-Centric IC Design Flow Architecture/Conceptual-level Design Design Specification Interconnect Planning • Physical Hierarchy Generation • Foorplan/Coarse Placement with Interconnect Planning • Interconnect Architecture Planning HDM abstraction Synthesis and Placement under Physical Hierarchy Structure view Functional view Physical view Timing view Interconnect Synthesis Performance-driven Global Routing Pseudo Pin Assignment under Noise Control Final Layout

Interconnect Optimization (TRIO) • Topology Optimization with • Buffer Insertion • Wire sizing and spacing • Simultaneous Buffer Insertion • and Wire Sizing • Simultaneous Topology Construction • with Buffer Insertion and Wire Sizing Interconnect Performance Estimation Models (IPEM) • OWS, SDWS, BISWS Interconnect Synthesis Performance-driven Global Routing Interconnect Optimization (TRIO) Interconnect Performance Estimation Models (IPEM) Pseudo Pin Assignment under Noise Control • Topology Optimization with Buffer Insertion • Wire sizing and spacing • Simultaneous Buffer Insertion and Wire Sizing • Simultaneous Topology Construction • with Buffer Insertion and Wire Sizing Interconnect Planning • OWS • SDWS • BISWS Route Planning • Physical Hierarchy Generation • Foorplan/Coarse Placement with • Interconnect Planning • Interconnect Architecture Planning Interconnect Layout Point-to-Point Gridless Routing Route Planning Point-to-Point Gridless Routing Interconnect Layout Overview of Interconnect-Centric IC Design Flow Architecture/Conceptual-level Design Design Specification Interconnect Planning • Physical Hierarchy Generation • Foorplan/Coarse Placement with Interconnect Planning • Interconnect Architecture Planning HDM abstraction Synthesis and Placement under Physical Hierarchy Structure view Functional view Physical view Timing view Interconnect Synthesis Performance-driven Global Routing Pseudo Pin Assignment under Noise Control Final Layout

Efficient (constant time) and accurate (90%) interconnect delay estimation models for 2-pin nets under different interconnect optimization algorithms [Cong-Pan, IWLS’98, SRC/TECHCON’98, ASPDAC’99] Interconnect architecture planning [Cong-Pan,DAC’99] Efficient and accurate interconnect estimation models for multiple-pin nets [Cong-Pan, TAU’99] Buffer block planning for interconnect-driven floorplanning [Cong-Kong-Pan, ICCAD’99] Review: Accomplishments in Year 1& 2

An improved crosstalk model with application to noise constrained interconnect optimization. [Cong-Pan-Srinivas, SRC Techcon’00, TAU’00] Pseudo pin assignment with crosstalk noise control [Chang-Cong, ISPD’00] Routing tree construction under fixed buffer locations [Cong-Yuan, DAC’00] Ongoing studies on physical planning Accomplishments and Ongoing Works in Year 3

Crosstalk Noise Aggressor net Cx Victim net

Previous Works • Transmission line equations [Sakurai+, TED’93, ASPDAC’98] • Only handle fully coupled bus lines • Devgan’s model [ICCAD’97] • Elegant, Elmore-like formula for peak noise • Over estimation, esp. when aggressor slew is small => could lead to noise even larger than Vdd ! • Charge-sharing based (e.g., [Vittal & Marek-Sodawska, TCAD’97]) • One lumped R, C for victim/aggressor net • Simple noise formulae for peak noise, and noise amplitude-width product • Cannot differ near-source versus near-sink coupling • Need simple yet accurate model that considers more KEY (but not more than necessary) parameters to guide layout optimization !

2- Crosstalk Noise Model [Cong-Pan-Srinivas, SRC Techcon’00, TAU’00] Aggressor net Cx Le Lc Ls Cl Victim net Tr Rd Rs Re Cs2 Cs1 Cl Ce1 Ce2

2- Model Tr Rd Rs Re Cs2 Cs1 Cl Ce1 Ce2 Rd Rs Re C1=Cs1 CL=Ce2+Cl C2=Cs2+Ce1

Let tx: RC delay from upstream resistance times coupling cap. tv: Elmore delay of the victim net Closed-Form Solutions • Peak noise • Noise width

Unified View for Existing Models (2-model) • Peak noise • As (Vittal+ TCAD’97 model) • As (Devgan ICCAD’97 model) • As (Vittal+ TCAD’99 model, Up to 100% larger than Devgan metric for large tr)

Experimental Results • 1,000 random nets based on realistic parameters

Applications of 2- Model • We have obtained a set of rules for noise reduction using different interconnect optimizations • Driver sizing • Near source versus sink coupling • Shield insertion • Wire sizing and spacing • AW product (noise amplitude • width) • Used in Magma’s BlastFusion software -- U.S. Patent Pending

Vias: 6 Vias: 8 Coupling: 2 Coupling: 4 Pseudo Pin Assignment with Crosstalk Noise Control • Pseudo pin: a point where a net crosses a tile boundary • Pseudo pin assignment: bridge between global routing and detailed routing • Our contributions: Pseudo pin assignment algorithm for gridless general area routing with noise control • Control crosstalk noise • Handle obstacle constraints • Align pseudo pins for detailed routing routability • Reduce the total wire length

Why Crosstalk Noise Control in Pseudo Pin Assignment • What can we do in routing to affect crosstalk? • Buffer insertion (if the global router does it) • Wire ordering • Wire spacing • Determine wire ordering and spacing • Global routing? High complexity, hard to consider obstacles • Detailed routing? Flexibility is low • Pseudo pin assignment? Reasonable complexity and high accuracy

Maximum strip boundary decomposition: Partition boundary to intervals One layer at a time Optimize one row at a time Coarse pseudo pin assignment: Assign pseudo pins to intervals Detailed assignment within each “strip”: Determine pseudo pin locations PPA Algorithm Overview

A Noise Distribution Example – After Detailed Routing • Test case: scaled mcc2, NTRS’97 0.18 um Tech, 0.3 Vdd noise constraints • Pseudo pin assignment with noise control effectively reduce crosstalk noise and meet noise constraints

source sink hard block or IP buffer block obstacle An Example of Floorplan with Buffer Block Planning Motivations for Routing Tree Construction under Fixed Buffer Locations • Given buffer blocks planned in early stage, how to do routing and buffer insertion under fixed buffer locations? • Investigate different buffer block planning schemes.

RMP (Recursively Merging and Pruning) Algorithm • Basic Idea: • A bottom-up tree construction combined with buffer insertion. • Generate a set of subtrees from sinks and then gradually expand and merge them until a complete tree with best performance is produced. • Key differences from previous approaches • The sets of subtrees may not be disjoint • Multiple subtrees may be generated at a node • Works on a routing graph • Handle multiple-pin nets with fixed buffer locations constraints.

Modify BA-tree algorithm [TRIO] to handle fixed buffer insertion (MBA-tree) Similar to the semi-automatic approach used in real design: “round” ideal buffers in BA-tree to the given buffers in MBA-tree. Comparison BetweenRMP and Modified BA-tree Algorithm Experimental results of RMP vs. BMA-tree (all data are normalized with respect to RMP). RMP can outperform MBA-tree by up to 50% in terms of delay with comparable wirelength.

An improved crosstalk model with application to noise constrained interconnect optimization. [Cong-Pan-Srinivas, SRC Techcon’00, TAU’00] Pseudo pin assignment with crosstalk noise control [Chang-Cong, ISPD’00] Routing tree construction under fixed buffer locations [Cong-Yuan, DAC’00] Further study on physical planning Accomplishments and Ongoing Works in Year 3

Ongoing Studies on Physical Planning • Motivation • Logical hierarchy is different to physical hierarchy • Planning based on logical hierarchy is limited by floorplanning on logical hierarchy • Planning based on physical hierarchy with performance driven geometric embedded partitioning shows good promises [Cong-Lim ICCAD’00] • Further study on interconnect planning in physical hierarchy

Example of Logic Hierarchy in Final Layout By courtesy of IBM (Tony Drumm)

Several Ongoing Efforts • Studies on the impacts of layer assignment • Studies on the congestion of global interconnect • A reasonable formulation for physical planning

Impacts of Layer Assignments on Delays • Delays estimated by IPEM for optimal buffer insertion and wire sizing • 0.13 um NTRS’97 technology • Delay reduction of changing wires from layers 1-2 to layers 7-8: • 0.5mm: 2% • 6.5mm: 40% • 27.5mm: 49% • The longer the wire, the more possible reduction by assigning to upper metals

Congestion Analysis – Efforts and Preliminary Results • Upper metal layers are used for long wires for reducing delays • Are there enough routing resource on upper metal layers? What is the trend? • How many long wires that need to be routed on upper metal layers? • How much space available on upper metal layers (Power and Clock nets are also competing)? • List of industrial contacts that we consulted: • IBM – Tony Drumm, John Darringer • Intel – Desmond Kirkpatrick, Mosur Mohan, Kris Konigsfeld • HP – Norman Chang

Layer Competition under Different Target Delays (Test case from IBM)

Problem Formulation for Physical Planning • Plan the following to achieve optimization goals: • Physical hierarchy with rough geometric information for identifying global interconnects • Retiming and pipelining • Layer assignment for global interconnects • Global net topology generation and congestion control • Buffer planning • … • Estimate and Optimize the following objectives: • Delay • Area • Power • Signal integrity

Development of efficient and accurate interconnect performance estimation models for interconnect-driven synthesis and planning(Completed - 30-Jun-1999) Development of interconnect architecture planning framework (Completed - 30-Jun-1999) Development of efficient algorithms for integrated interconnect planning & floorplanning capabilities at the physical level (Completed- 30-Sep-1999) Development & validation of accurate noise models to guide the interconnect synthesis algorithm for signal reliability (Completed -31-Dec-1999) Development of optimal or near-optimal interconnect synthesis algorithm for multiple spatially or temporally related signal nets forperformance & signal reliability optimization (Completed - 31-Dec-1999) Development of efficient algorithms for integrated interconnect planning & floorplanning capabilities at the RTL-level; Software(Planned - 31-Dec-2000) Deliverables

TRIO (Tree-Repeater-Interconnect-Optimization) package Integrated into Intel design technology http://cadlab.cs.ucla.edu/~trio IPEM (Interconnect Performance Estimation Model) package Integrated into IBM design technology http://cadlab.cs.ucla.edu/software_release/ipem/htdocs Wire width planning U.S. Patent pending under SRC sponsorship BBP (Buffer Block Planning) for physical level floorplanning Source code transferred to IBM Interests from Intel and HP Crosstalk noise modeling U.S. Patent pending (joint with Magma) Technology Transfer

An improved crosstalk model with application to noise constrained interconnect optimization. Pseudo pin assignment with crosstalk noise control Routing tree construction under fixed buffer locations Ongoing studies on physical planning Summary

Development of a computational model for interconnect architecture planning based on a given design characterization (specified interms of target clock rate, interconnect distribution, depths of logic,network, etc.) (31-Dec-1998) Development of estimation models for interconnect layout optimizations suitable for pre-layout synthesis and planning(31-Dec-1998) Development of efficient algorithms for integrated interconnect planning and floorplanning capabilities at the RTL-level(31-Dec-1999) Completion of the ongoing effort on the development on a multi-layer general-area gridless routing system (31-Dec-1999) Development of optimal or near-optimal interconnect synthesis algorithm for multiple spatially or temporally related signal nets forperformance and signal reliability optimization (31-Dec-1999) Development and validation of very efficient but accurate noise models to relate the noise with the physical parameters to guide theinterconnect synthesis algorithm for signal reliability optimization (31-Dec-1999) Development of efficient algorithms for integrated interconnect planning and floorplanning capabilities at the physical level(31-Dec-1999) Development of efficient algorithms for integrated interconnect planning and floorplanning capabilities at the RT-level(31-Dec-2000) Milestones

PI: Prof. Jason Cong (UCLA) Graduate Students: Chin-Chih Chang, David Pan, Xin Yuan