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SigRace: Signature-Based Data Race Detection

SigRace: Signature-Based Data Race Detection

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SigRace: Signature-Based Data Race Detection

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  1. SigRace: Signature-Based Data Race Detection Abdullah Muzahid, Dario Suarez*, Shanxiang Qi & Josep Torrellas Computer Science DepartmentUniversity of Illinois at Urbana-Champaignhttp://iacoma.cs.uiuc.edu *Universidad de Zaragoza, Spain

  2. Debugging Multithreaded Programs “Debugging a multithreaded program has a lot in common with medieval torture methods” -- Random quote found via Google search

  3. T1 T2 lock L x++ unlock L x++ Data Race • Two threads access the same variable without intervening synchronization and at least one is a write • Common bug • Hard to detect and reproduce

  4. Dynamic Data Race Detection • Mainly two approaches

  5. Dynamic Data Race Detection • Mainly two approaches • Lockset: Finds violation of locking discipline

  6. Dynamic Data Race Detection • Mainly two approaches • Lockset: Finds violation of locking discipline • Happened-Before: Finds concurrent conflicting accesses

  7. Happened-Before Approach

  8. Happened-Before Approach Thread 0 Thread 1 [0, 0] [0, 0]

  9. Happened-Before Approach Thread 0 Thread 1 [0, 0] [0, 0] Lock L [1, 0]

  10. Happened-Before Approach Thread 0 Thread 1 [0, 0] [0, 0] Lock L [1, 0] Unlock L [2, 0]

  11. Happened-Before Approach Thread 0 Thread 1 [0, 0] [0, 0] Lock L [1, 0] Unlock L [2, 0]

  12. Happened-Before Approach Thread 0 Thread 1 [0, 0] [0, 0] Lock L [1, 0] Unlock L [2, 0] Lock L

  13. Happened-Before Approach Thread 0 Thread 1 [0, 0] [0, 0] Lock L [1, 0] [0, 1] Unlock L [2, 0] Lock L

  14. Happened-Before Approach Thread 0 Thread 1 [0, 0] [0, 0] Lock L [1, 0] [0, 1] Unlock L [2, 0] + Lock L [2, 1]

  15. Happened-Before Approach Thread 0 Thread 1 [0, 0] [0, 0] • Epoch : sync to sync Lock L [1, 0] Unlock L [2, 0] Lock L [2, 1]

  16. Happened-Before Approach Thread 0 Thread 1 a [0, 0] [0, 0] • Epoch : sync to sync d Lock L b [1, 0] Unlock L [2, 0] c Lock L [2, 1] e

  17. Happened-Before Approach Thread 0 Thread 1 a [0, 0] [0, 0] d Lock L b [1, 0] Unlock L [2, 0] c Lock L [2, 1] e • Epoch : sync to sync

  18. Happened-Before Approach Thread 0 Thread 1 a [0, 0] [0, 0] d Lock L b [1, 0] Unlock L [2, 0] c Lock L [2, 1] e • Epoch : sync to sync

  19. Happened-Before Approach Thread 0 Thread 1 a [0, 0] [0, 0] d Lock L b [1, 0] Unlock L [2, 0] c Lock L [2, 1] e • Epoch : sync to sync

  20. Happened-Before Approach Thread 0 Thread 1 a [0, 0] [0, 0] d Lock L b [1, 0] Unlock L [2, 0] c Lock L [2, 1] e • Epoch : sync to sync • a, b happened before e

  21. Happened-Before Approach Thread 0 Thread 1 a [0, 0] [0, 0] d Lock L b [1, 0] Unlock L [2, 0] c Lock L [2, 1] e • Epoch : sync to sync • a, b happened before e

  22. Happened-Before Approach Thread 0 Thread 1 a [0, 0] [0, 0] d Lock L b [1, 0] Unlock L [2, 0] c Lock L [2, 1] e • Epoch : sync to sync • a, b happened before e • c, d unordered

  23. Happened-Before Approach Thread 0 Thread 1 a [0, 0] [0, 0] d Lock L = x b [1, 0] Data Race Unlock L [2, 0] c Lock L [2, 1] x = e • Epoch : sync to sync • a, b happened before e • c, d unordered

  24. Software Implementation • Need to instrument every memory access • 10x – 50x slowdown • Not suitable for production runs

  25. Hardware Implementation

  26. P1 P2 Hardware Implementation … … C1 C2

  27. P1 P2 Hardware Implementation … … C1 C2 TS TS

  28. P1 P2 Hardware Implementation ts1 x … … C1 C2 TS TS

  29. P1 P2 Hardware Implementation WR ts1 x ts2 x … … C1 C2 TS … TS ts2

  30. P1 P2 Hardware Implementation check WR ts1 x ts2 x ts2 … … C1 C2 TS … TS ts2

  31. Limitations of HW Approaches

  32. Limitations of HW Approaches P1 P2 • Modify cache and coherence protocol C1 … … C2 …

  33. Limitations of HW Approaches P1 P2 check • Modify cache and coherence protocol • Perform checking at least on every coherence transaction ts1 C1 … … C2 ts2 … ts2

  34. Limitations of HW Approaches P1 P2 • Modify cache and coherence protocol • Perform checking at least on every coherence transaction • Lose detection ability when cache line is displaced or invalidated C1 … … C2

  35. Our Contributions • SigRace: Novel HW mechanism for race detection based on signatures • Simple HW • Cache and coherence protocol are unchanged • Higher coverage than existing HW schemes • Detect races even if the line is displaced/invalidated • Usable on-the-fly in production runs • SigRace finds 150% more injected races than a state-of-the-art HW proposal

  36. Outline • Motivation • Main Idea • Implementation • Results • Conclusions

  37. Main Idea Address Signature + Happened-before

  38. ROB ld/st … address … Permute [Ceze et al, ISCA06] Hardware Address Signatures

  39. Hardware Address Signatures

  40. Hardware Address Signatures • Logical AND for intersection • Has false positives but not false negatives

  41. sync Epoch sync Using Signatures for Race Detection

  42. Epoch Using Signatures for Race Detection sync TS Sig sync

  43. Epoch Using Signatures for Race Detection sync • Block is a fixed number of dynamic instructions (not a cache block or basic block or atomic block) Block TS1 Sig1 sync

  44. Epoch Using Signatures for Race Detection sync Block TS1 Sig1 sync Race Detection Module

  45. Epoch Using Signatures for Race Detection sync Block TS1 Ø sync Race Detection Module

  46. Epoch Using Signatures for Race Detection sync Block TS1 Sig2 sync Race Detection Module

  47. Epoch Using Signatures for Race Detection sync Block TS1 Sig2 sync Race Detection Module

  48. Epoch Using Signatures for Race Detection sync Block TS1 Ø sync Race Detection Module

  49. Epoch Using Signatures for Race Detection sync sync Block TS2 Sig3 Race Detection Module

  50. Epoch Using Signatures for Race Detection sync sync Block TS2 Sig3 Race Detection Module