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Development & Evolution: Hardware Support and Encouragement

Development & Evolution: Hardware Support and Encouragement. Andy M. Tyrrell University of York, Department of Electronics, Bio-inspired Architectures Lab,.

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Development & Evolution: Hardware Support and Encouragement

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  1. Development & Evolution: Hardware Support and Encouragement Andy M. Tyrrell University of York, Department of Electronics, Bio-inspired Architectures Lab,

  2. Evolvable hardware is the field that brings together reconfigurable hardware, artificial intelligence, fault tolerance and autonomous systems. Evolvable hardware refers to hardware that can change its architecture and behaviour dynamically and autonomously by interacting with its environment. Ideally this process of interactions and changes should be a continuous one and should be open-ended. Evolved hardware is the field that brings together reconfigurable hardware, artificial intelligence, fault tolerance and autonomous systems. Evolved hardware refers to hardware that has been created through a process of continued refinement and stops when a sufficiently “good” individual has been found.

  3. COTS digital reconfigurable hardware PLA  FPGA  Virtex, VirtexII, VirtexPro (Xilinx)

  4. Adrian Thompson’s initial work Frequency discrimination Interesting use of “digital” circuits

  5. Artificial evolution for design Evolved Hardware Evolution of digital function - of the order of a few 100 gates

  6. Programmable Transistor Array Cell - FPTA2 Cell Schematic Chip Architecture

  7. Using JPL technology: Evolved 4-bit DAC inputs (In1, In2 and In3 [In4 not shown]) and output (O4).

  8. FPTA from Heidelberg Programmable channel lengths & connectivity 16x16 array

  9. Using FPTA technology Voltage characteristics of the best evolved logic gates (AND, OR, XOR)

  10. Artificial evolution for design - revisited Evolution of digital function - of the order of a few 100 gates Let’s be generous and assume each gate consists of 100 transistors - eg 10,000 transistors

  11. Current technology

  12. Faults and degradation in extreme environments Evolution can recover functionality of circuits affected by faults and degradation, by finding a new circuit bypassing the fault or using damaged components in a different configuration. Experiments at low (-196C) and high (>+300C) demonstrate that electronic functions altered by temperature can be recovered through reconfiguration (JPL).

  13. Fault-tolerance

  14. Development?

  15. Multi-cellular Organisms possess All cells come from a single special one (zygote), and this process is named development in biology.

  16. CU CU CU EU EU EU Cell (1,1) Cell (1,2) Cell (1,2) CU CU CU EU EU EU (2,2) (2,3) Cell Cell Cell (2,1) CU Control Unit EU Execution Unit EU Function Selection States Signals CU CU CU Cell border Executing Signals EU EU EU (3,2) (3,3) Cell Cell Cell (3,1) Development Cellular Array Model Inter-connection of Cells

  17. NSCG Next States & Chemical Generator SR Cell States & Chemical Register States & Chemical Signals from neighbors States & Chemical Signals of this cell Intra-cell Signals EUFS EU Function Selection NIN NOUT WIN NSCG EIN SR WOUT EOUT EUFS SIN SOUT Control Unit Structure

  18. NSG Next States Generator NCG Next Chemical Generator States Signals from neighbors Chemical Signals from neighbors Chemical of this cell State of this cell States IN NSG Next State NCG Chemicals IN Next Chemical Current State Current Chemical NSCG Structure

  19. Initialize chemical and the zygote; Chemical diffusion; All cells update their state simultaneously: If no chemical at a position or all the cell’s 4 neighbors and itself are dead (state is 0), then this cell’s internal program will not be executed; Otherwise, executing its program, which will generate its next time chemical and state based on current states and chemicals; a. If next state generated is alive, then overwrite chemical at this position with its own generated chemical; b. Otherwise, do not touch the chemical at this position; Unless stopping criterion reached go to 2. Cell Growth

  20. Chemical diffusion is the means by which cells can send long-distance messages to other ones. The rule is: Chemical DiffusionDetails

  21. CU CU CU A[0] & B[0] EU EU EU Cell (1,1) Cell (1,2) Cell (1,2) CU CU CU A[1] & B[1] R[0] & R[1] EU EU EU (2,2) (2,3) Cell Cell Cell (2,1) WEST CU CU CU R[2] & R[3] EU EU EU (3,2) (3,3) Cell Cell Cell (3,1) Legends SOUTH CU Control Unit EU Execution Unit EU Function Selection State (2bits) & Chemical (4bits) Cell border Executing Signals (3-bit width) A & B The multiplier inputs R Result output of the multiplier 3x3 Cells Organism

  22. EUC M EUC Execution Unit Core Executing Signals (3-bit) Multiplexer EU Function Selection (2-bit) (The state of this cell) EU border Execution Unit Structure

  23. Another injected Developmental Growth A set of faults injected Overview of the Simulation Waveform

  24. Developmental Growth

  25. Top-level Overview of the Intrinsic Evolvable Hardware Platform

  26. Synthesis Report Overall: 31.9% LUTs, 3.77% Flip Flops, 58.6% IOBs

  27. The Intrinsic Robust Transient Fault-Tolerant Developmental Model can be applied to real-world applications. In hardware implementation the model still can exhibit its intrinsic fault tolerant characteristics. Still difficult to implement on COTS devices. Summary

  28. POEtic www.poetictissue.org

  29. Goals of the POEtic project • Development of a flexible computational substrate inspired by the evolutionary, developmental and learning phases in biological systems • Construction of a multi-cellular electronic tissue with Phylogenetic, Epigenetic and Ontogenetic capabilities

  30. POEtic Architecture

  31. POEtic Organic Subsystem Structure Routing Layer Molecular Layer

  32. Molecule Modes 16/8-bit LUT Arithmetic Shift Memory Cellular Input Cellular Output Configure Trigger Communication

  33. Partial Reconfiguration • 76 Configuration bits of a molecule are split in 5 blocks • Each block can be reconfigured by a neighbor molecule • Serial access • Allows a cell to • reconfigure another one • differentiate • store a genome (up to 54 bits per molecule)

  34. Mode partial LUT inputs Others LUT Switchbox Configuration String partial partial partial partial LUT LUT inputs Switchbox Mode Others partial partial partial partial partial Configuration String Molecule Configuration Chain Full configuration Partial configuration Molecule Configuration Register

  35. Partial Reconfiguration • Molecules can modify configuration bits of other molecules • Serial access • Long distance

  36. Routing Plane • A distributed routing algorithm is implemented • 4 molecules connected to 1 routing unit • Allows to: • Create connections at runtime • Without global control • Connect cells over different chips • Allows implementation of growth and self-repair mechanisms

  37. Multichip designs • The routing plane allows to connect chips together • The number of lines passing through pads has been reduced

  38. I O Dynamic Routing Layer Routing Layer Routing Unit Data In Input Molecule Cell Data Out Molecule Molecular Layer Output Molecule Cell

  39. Summary of Design • POEtic contains new features: • Dynamic routing • Connection of cells at runtime • Useful for evolution, growth and self-repair…? • Molecular partial self-reconfiguration • Useful for differentiation and genome storing…? • No possibility of short-circuits • Allows POEtic to be used for unconstrained evolvable hardware

  40. The Device!

  41. system bus Environment subsystem sensors actuators System interface I to other POEtic chips Organic subsystem O to other POEtic chips POEtic chip Organisation of the POEtic chip P mechanisms O and E mechanisms

  42. AHB Bus APB Bus APB bridge AHB bus controller mP core Communications unit External memory unit Environment subsystem 16 x 16 booth mult. 16-bit timer Clock manager 16-bit timer Configuration unit (System Interface) Organic subsystem Overall description of the chip - Organisation

  43. Test board • Goals: • Test the POEtic chips • Development of applications • Overall features: • 16 MB Flash • 128 MB DRAM • USB controller for communication with the host terminal • Programmable clock frequency (organic & environment subsystems) • FPGA for DRAM control and system debugging • Organisation: • Master board with the master POEtic chip • Slave boards containing 4 POEtic chips permit to configure a POEtic matrix using 2x2 sub-matrices

  44. Test board details MASTER SLAVES DRAM Flash

  45. Using POEtic?

  46. Universal Spare Cells Initialized Tissue Cell routed and working Fault Detected :- Working cell connects to spare cell Working cell configures spare cell masking faulty configuration and data New cell routed and working Initialized Working Cell Frame 1 Frame 5 Frame 3 Frame 4 Frame 2 Artificial Cell Structures on the POEtic Tissue “Growth” Cell Life-Cycle Etc.

  47. Final Remarks!

  48. First device including P, O and E capabilities First device including partial dynamic configuration, self-configuration and dynamic routing capabilities First actual autonomous self-configurable device (evolution + self-configuration and dynamic routing) POEtic tissue as an electronic device

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