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Universidade Federal de Santa Catarina Centro Tecnológico

Universidade Federal de Santa Catarina Centro Tecnológico Computer Science & Electrical Engineering. Digital Integrated Circuits INE 5442 / EEL 7312. Lectures 33 to 36 Combinational Circuits in CMOS. Prof. José Luís Güntzel guntzel@inf.ufsc.br. Agenda. Complementary CMOS

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Universidade Federal de Santa Catarina Centro Tecnológico

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  1. Universidade Federal de Santa Catarina Centro Tecnológico Computer Science &Electrical Engineering Digital Integrated Circuits INE 5442 / EEL 7312 Lectures 33 to 36 Combinational Circuits in CMOS Prof. José Luís Güntzel guntzel@inf.ufsc.br

  2. Agenda • Complementary CMOS • Pass-Transistor Logic 2

  3. Combinational Logic out0 out1 ... outn Combinational Logic in0 in1 ... inm out0 out1 ... outj in0 in1 ... ink State Combinational vs. Sequential Logic Output values depend only on the current input values (no feedback, no storage element). Output values depend on the current input values and on previous input values(feedback with/without storage element). 3

  4. Logic Families in CMOS • Static CMOS Logic • Complementary CMOS • Ratioed Logic • Pass-Transistor Logic • Dynamic CMOS Logic 4

  5. Metrics for Choosing a Gate Design/Family • Area in silicon (related to number of transistors) • Speed (propagation delay) • Energy consumption/Power dissipation • Robustness to noise • Reliability • Manufacturability “Depending on the application, the emphasis will be on different metrics.” (Rabaey; Chandrakasan; Nikolic, 2005) 5

  6. Static CMOS Logic • Features: • Robustness (low sensitivity to noise). • Good performance. • Low power consumption (no static consumption, except for leakage currents). • Easy to design (good for novice designers…) 6

  7. Vdd in out Complementary Logic: the inverter Logic-level symbol Transistor schematics in out Truth-table 7

  8. Complementary Logic: mask layout for an inverter Gnd N channel P channel Vdd N P N P P well N Substrate P-implant N-implant 8

  9. Vdd in=0 out=1 CL= Vdd Vdd in=1 out=0 (in=Vdd) CL= 0 V Complementary Logic: the inverter Steady-state operation • Transistors seemed as idealelectronic switches • Capacitance represents the total charge at the gate´s output 9

  10. Vdd PMOS only makes f(in1, in2, in3) = 1 in1 in2 in3 pull-up network out = f(in1, in2, in3) NMOS only makes f(in1, in2, in3) = 0 pull-down network in1 in2 in3 GND Complementary Logic • Pull-up and pull-down networks are mutually exclusive transistor associations (dual) • In steady state, there is always a path to either Vdd or GND! (In steady state, the output is always a low-impedance node.) 10

  11. Vdd  0 Vdd  |VTp| output output D S CL CL Vdd S D Vdd Vdd D S Vdd 0  Vdd - VTn output S D output 0  Vdd CL CL Static CMOS Logic Discharging the output capacitance… VGS Charging the output capacitance… VGS 11

  12. X A B Y NMOS Series/Parallel Associations control variables X control variables A B Y X=YifA=1ORB=1 X=YifA=1ANDB=1 Problem: NMOS transistors pass a weak “1” (but a strong “0”) 12

  13. X A B Y PMOS Series/Parallel Associations control variables control variables X A B Y X=YifA=0ORB=0 X=YifA=0ANDB=0 Problem: PMOS transistors pass a weak “0” (but a strong “1”) 13

  14. Vdd PMOS only; makes f(in1, in2, in3) = 1 in1 in2 in3 pull-up network out = f(in1, in2, in3) NMOS only; makes f(in1, in2, in3) = 0 pull-down network in1 in2 in3 GND Complementary Logic • Only negative logic functions are implemented (e.g.: inverter, NAND, NOR, XNOR…) • Design procedure: • use the “0” of the gate function to design the pull-down network • Apply De Morgan´s theorem to find the pull-up network. • An n-input logic gate requires 2n transistors. 14

  15. Vdd B A A S S B A B Complementary Logic: 2-input Nand Logic-level symbol Transistor schematics Truth-table 15

  16. V DD Vdd B A S A B Complementary Logic: 2-input Nand mask layout A B Out GND 16

  17. Vdd Vdd B=1 B=0 A=0 A=0 S=1 S=1 A=0 A=0 CL=Vdd CL=Vdd B=1 B=0 Vdd Vdd B=0 B=1 A=1 A=1 S=1 S=0 A=1 A=1 CL=Vdd CL=0 V B=0 B=1 Complementary Logic: 2-input Nand Steady state behavior: 4 possible input combinations 17

  18. A A S B B S tpLH(A) tpLH(B) tpHL(A) tpHL(B) Complementary Logic: 2-input Nand Delay characterization through electric-level simulation (e.g., Spice) Evaluates the individual contribution of each input (the others are kept at their non-controlling values) 18

  19. V DD Vdd B A S A B Complementary Logic: 2-input Nand A B Out GND 19

  20. Vdd A S B B A S B A Complementary Logic: 2-input Nor Logic-level symbol Transistor schematics Truth-table 20

  21. Building Complementary CMOS Complex Gates Example: S = A+B·C If the logic gate equation is not negated, imagine it as it were. At the end, an extra inverter will have to be added . (Alternatively, apply De Morgan´s theorem…) Take the non-inverting equation of the logic gate to design the pull-down network S B A C 21

  22. Vdd B C A S B A C Building Complementary CMOS Complex Gates Example: S = A+B·C • Design the pull-up network by finding the dual of the pull-down network, already designed: • Each series NMOS association gives rise to a parallel PMOS association • Each parallel NMOS association gives rise to a series PMOS association 22

  23. Properties of Complementary CMOS Gates • Full rail-to-rail swing; high noise margins (VOH=Vdd , VOL=GND) • Logic levels not dependent upon the relative device sizes;ratioless • Always a path to Vdd or Gnd in steady state; low output impedance • Extremely high input resistance; nearly zero steady-state input current • No direct path steady state between power and ground; no static power dissipation • Propagation delay function of load capacitance and resistance of transistors Source: Rabaey; Chandrakasan; Nikolic, 2005 23

  24. Rp Rp Rp B A B Rp Rp Rp A Cint Rn A CL CL CL B Rn A Rn Rn Rn Cint A B A Switch Delay Models for Complementary Gates NAND2 INV NOR2 Source: Rabaey; Chandrakasan; Nikolic, 2005 24

  25. Rp Rp A B Rn CL B Rn Cint A Delay Depends on the Input Pattern • Delay is dependent on thepattern of inputs • Low to high transition • both inputs go low • delay is 0.69 Rp/2 CL • one input goes low • delay is 0.69 Rp CL • High to low transition • both inputs go high • delay is 0.69 2Rn CL Source: Rabaey; Chandrakasan; Nikolic, 2005 25

  26. Delay Depends on the Input Pattern NMOS = 0.5m/0.25 m PMOS = 0.75m/0.25 m CL = 100 fF Sized for tpLH =~ tpHL A=B=10 A=1 0, B=1 Voltage [V] A=1, B=10 time [ps] Source: Rabaey; Chandrakasan; Nikolic, 2005 26

  27. Vdd B=1 A=1 S=0 B=1 Cint=0 V CL=0 V A=1 Vdd B=1 A=0 S=1 Vdd-VTn B=1 CL=Vdd A=0 Delay Depends on the Input Pattern NMOS = 0.5m/0.25 m PMOS = 0.75m/0.25 m CL = 100 fF Sized for tpLH =~ tpHL A=B=10 A=1 0, B=1 Voltage [V] A=1, B=10 time [ps] Source: Rabaey; Chandrakasan; Nikolic, 2005 27

  28. Vdd B A S B A The “Body Effect” • The VT of the two NMOS transistors are calculate by: VTn2 = Vtn0 +  (( 2f+ Vint)0.5 – (2f)0.5) M2 VTn1 = Vtn0 int M1 Source: Rabaey; Chandrakasan; Nikolic, 2005 28

  29. R5 R7 R6 R8 C A B D R4 A R3 B C3 C1 C2 CL R2 C R1 D Transistor Sizing Considering intra-cell capacitances Distributed RC model (“Elmore Delay”) tpHL = 0,69  (R1C1+ (R1+R2)  C2 + + (R1+R2+R3)  C3 + (R1+R2+R3+R4)  CL) If R1=R2=R3=R4 then: tpHL = 0.69 Reqn(C1+2C2+3C3+4CL) 29

  30. quadratic tp (ps) tpHL tp tpLH linear fanin Propagation Delay as a Function of Fan-In Propagation delay of CMOS NAND gate Gates with more than 4 inputs should be avoided… Source: Rabaey; Chandrakasan; Nikolic, 2005 30

  31. Propagation Delay as a Function of Fan-Out tpNOR2 tpNAND2 All gates have the same drive current. tpINV tp (psec) Slope is a function of “driving strength” eff. fan-out Source: Rabaey; Chandrakasan; Nikolic, 2005 31

  32. Propagation Delay as a Function of Fan-Out • Fan-in: quadratic due to increasing resistance and capacitance • Fan-out: each additional fan-out gate adds two gate capacitances to CL tp = a1FI + a2FI2 + a3FO Source: Rabaey; Chandrakasan; Nikolic, 2005 32

  33. InN MN C3 C2 C1 CL In3 M3 In2 M2 In1 M1 Design Techniques for Static CMOS Gates • Transistor sizing • Desde que a capacitância de saída domine • Progressive sizing RC distribuído WM1 > WM2 > WM3 > … > WMN (o trans. mais próximo da saída tema a menor resistência de canal.) Pode reduzir o atraso da porta em até 20% (segundo Rabaey) Source: Rabaey; Chandrakasan; Nikolic, 2005 33

  34. C2 C1 C2 C1 CL CL Design Techniques for Static CMOS Gates Transistor ordering Critical path Critical path 01 charged 1 In1 charged In3 M3 M3 1 1 In2 In2 M2 charged M2 charged 1 In3 In1 M1 charged M1 charged 01 O Atraso é determinado pelo tempo para descarregar CL O Atraso é determinado pelo tempo para descarregar CL, C1 e C2 Source: Rabaey; Chandrakasan; Nikolic, 2005 34

  35. Design Techniques for Static CMOS Gates • Explorando a Decomposição Lógica F = ABCDEFGH Elevando fanin (evitar) Lógica de 2 níveis em CMOS Faninlimitado a 2, fanout unitário Source: Rabaey; Chandrakasan; Nikolic, 2005 35

  36. CL CL Design Techniques for Static CMOS Gates • Isolamento de carga elevada usando buffer Source: Rabaey; Chandrakasan; Nikolic, 2005 36

  37. Cell Design • Standard Cells • General purpose logic • Can be synthesized • Same height, varying width • Datapath Cells • For regular, structured designs (arithmetic) • Includes some wiring in the cell • Fixed height and width Source: Rabaey; Chandrakasan; Nikolic, 2005 37

  38. Standard Cell Layout Methodology – 1980s Routing channel VDD signals GND Source: Rabaey; Chandrakasan; Nikolic, 2005 38

  39. Standard Cell Layout Methodology – 1990s Mirrored Cell No Routing channels VDD VDD M2 M3 GND Mirrored Cell GND Source: Rabaey; Chandrakasan; Nikolic, 2005 39

  40. V DD Standard Cells N Well Cell height 12 metal tracks Metal track is approx. 3 + 3 Pitch = repetitive distance between objects Cell height is “12 pitch” Out In 2 Rails ~10 GND Cell boundary Source: Rabaey; Chandrakasan; Nikolic, 2005 40

  41. V V DD DD Standard Cells With minimaldiffusionrouting With silicided diffusion Out In Out In GND GND Source: Rabaey; Chandrakasan; Nikolic, 2005 41

  42. V DD Standard Cells 2-input NAND gate A B Out GND Source: Rabaey; Chandrakasan; Nikolic, 2005 42

  43. V V DD DD Stick Diagrams Contains no dimensions Represents relative positions of transistors Inverter NAND2 Out Out In A B GND GND Source: Rabaey; Chandrakasan; Nikolic, 2005 43

  44. X PUN C i VDD X B A j PDN GND Stick Diagrams Logic Graph A j C B X = C • (A + B) C i A B A B C Source: Rabaey; Chandrakasan; Nikolic, 2005 44

  45. Two Versions of C • (A + B) A C B A B C VDD VDD X X GND GND Source: Rabaey; Chandrakasan; Nikolic, 2005 45

  46. Consistent Euler Path X C i VDD X B A j A B C GND Source: Rabaey; Chandrakasan; Nikolic, 2005 46

  47. OAI22 Logic Graph X PUN A C D C B D VDD X X = (A+B)•(C+D) C D B A A B PDN A GND B C D Source: Rabaey; Chandrakasan; Nikolic, 2005 47

  48. Multi-Fingered Transistors One finger Two fingers (folded) Less diffusion capacitance Source: Rabaey; Chandrakasan; Nikolic, 2005 48

  49. A’ E1 saída B’ E2 A B Pass Transistor Logic Exemplo 1: uma função arbitrária (com 4 vars. de controle) buffer Saída = ABE2’+A’E1’+B’E1’ • N transistores • Sem consumo estático 49

  50. O Comportamento do Transistor de Passagem 3.0 In Out 2.0 x Tensão [V] 1.0 0.0 0 0.5 1 1.5 2 Tempo [ns] • Vx não consegue atingir Vdd, masVdd -VTn(Vx) (efeito de corpo) • Tensão na entrada do inversor não é suficiente para desligar o transistor PMOS • Mensagem: não cascatear transistores de passagem, conectando-os a gates de outras estruturas similares. ~ Source: Rabaey; Chandrakasan; Nikolic, 2005 50

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