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Wireless Embedded Systems Aaron Schulman

CSE190 Winter 2019 Lecture 5 Direct Memory Access. Wireless Embedded Systems Aaron Schulman. Why do we need DMA?. Why do we need DMA?. Polling and Interrupt driven I/O concentrates on data transfer between the processor and I/O devices.

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Wireless Embedded Systems Aaron Schulman

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  1. CSE190 Winter 2019 Lecture 5 Direct MemoryAccess Wireless Embedded Systems Aaron Schulman

  2. Why do we need DMA?

  3. Why do we need DMA? • Polling and Interrupt driven I/O concentrates on data transfer between the processor and I/O devices. • An instruction to transfer (mov datain,R0) only occurs after the processor determines that the I/O device is ready • Either by polling a status flag in the device interface or • Waits for the device to send an interrupt request. • Considerable overhead is incurred, because several program instructions must be executed for each data word transferred.

  4. Why do we need DMA? • Instructions are needed to increment memory address and keeping track of work count. • With interrupts, additional overhead associated with saving and restoring the program counter and other state information.

  5. Direct Memory Access (DMA) • To transfer large blocks of data at high speed, an alternative approach is used. • Blocks of data are transferred between an external device and the main memory, without continuous intervention by the processor.

  6. DMA Controller • DMA controller is part of the I/O interface. • Performs the functions that would normally be carried out by the processor when access main memory. For each word transferred, it provides the memory address and all the bus signals that control data transfer.

  7. DMA Controller • Device wishing to perform DMA asserts the processors bus request signal. • Processor completes the current bus cycle and then asserts the bus grant signal to the device. • The device then asserts the bus grant ack signal. • The DMA device performs the transfer from the source to destination address. • Once the DMA operations have been completed, the device releases the bus by asserting the bus release signal. • Processor acknowledges the bus release and resumes its bus cycles from the point it left off.

  8. Use of DMA Controllers 2. DMA controller requests transfer to memory RAM GPIOs Bus control logic DMA controller 4. ACK 5. Interrupt when done 3. Data is transferred Processor Storage 1. CPU programs the DMA controller

  9. How is OS involved • I/O operations are always performed by the OS in response to a request from an application program. • OS is also responsible for suspending the execution of one program and starting another. • OS puts the program that requested the transfer in the Blocked state, • initiates the DMA operation, • starts execution of another program. • When the transfer is complete, the DMA controller informs the processor by sending an interrupt request. • OS puts suspended program in the Runnable state so that it can be selected by the scheduler to continue execution.

  10. Linear logical memory

  11. Memory Architecture

  12. Main memory 0: Main memory CPU chip Physical address (PA) 1: 0: Address translation Virtual address (VA) Physical address (PA) 2: 1: 3: 2: CPU MMU 3: CPU 4: 4 4: 5: 4100 4 5: 6: 6: 7: 7: 8: ... ... M-1: M -1: Data word Data word Physical vs Virtual Memory • Two memory “spaces” • Virtual memory space ­ what the program “sees” • Physical memory space ­ what the program runs in (size of RAM) • Virtual memory requires • Dedicated hardware on CPU chip called Memory Mgmt Unit (MMU) • Cooperation between CPU hardware & operating system Source: Bryant & O’Hallaron

  13. Example: Virtual and Physical Address Space 0x00 0x04 0x08 0x0C 0x10 0x14 0x18 0x1C add r1,r2,r3 0x00 0x04 0x08 0x0C add r1,r2,r3 sub r2,r3,r4 sub r2,r3,r4 lw r2, 0x04 lw r2, 0x04 mult r3,r4,r5 mult r3,r4,r5 bne 0x00 add r10,r1,r2 sub r3,r4,r1 sw r5,0x0c

  14. Cache coherency problems • Imagine a CPU equipped with a cache and an external memory that can be accessed directly by devices using DMA. When the CPU accesses location X in the memory, the current value will be stored in the cache. Subsequent operations on X will update the cached copy of X, but not the external memory version of X, assuming a write-back cache. If the cache is not flushed to the memory before the next time a device tries to access X, the device will receive a stale value of X.

  15. Buffers and Arbitration • Most DMACs have a data storage buffer – network interfaces receive data from main memory at bus speed, send data onto network at network speed. • Bus Arbitration is needed to resolve conflicts with more than one device (2 DMACs or DMA and processor, etc..) try to use the bus to access main memory.

  16. Bus Arbitration • Bus Master – the device that is allowed to initiate bus transfers on the bus at any given time. When the current master relinquishes control, another device can acquire this status. • Bus Arbitration – the process by which the next device to become bus master is selected and bus mastership is transferred to it.

  17. Arbitration Approaches • Centralized – a single arbiter performs the arbitration. • Distributed – all devices participate in the selection of the next bus master.

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