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Extreme Makeover of System Design Science

Extreme Makeover of System Design Science. Daniel Gajski Center for Embedded Computer Systems (CECS) University of California, Irvine gajski@uci.edu. History of design flow. Design Gap: HW, SW, Application Real gap: behavior and structure (semantics and syntax).

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Extreme Makeover of System Design Science

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  1. Extreme MakeoverofSystem Design Science Daniel Gajski Center for Embedded Computer Systems (CECS) University of California, Irvine gajski@uci.edu

  2. History of design flow Design Gap: HW, SW, Application Real gap: behavior and structure (semantics and syntax)

  3. Simulation based methodology Ambiguous semantics of hardware/system level languages Simuletable but not synthesizable or verifiable

  4. Arithmetic algebra < objects, operations> Arithmetic algebra allows creation of expressions and equations

  5. Model algebra <objects, compositions> Model algebra allows creation of models and model equivalences

  6. Methodology based on model algebra Algebra := < {objects}, {operations} > Model algebra := < {objects}, {compositions} > Refinement is an ordered set of model transformations < tm, … , t2, t1> if and only if model B = tm( … ( t2( t1( model A ) ) ) … ) Design methodology := < {models}, {refinements} > Question: { models }? ; { transformations }?

  7. Why Model Algebra? • Defines SL semantics • Defines SL languages and styles • Identifies SL methodology • Enables SL design automation 5. Closes SW-HW gap 6. Introduces interoperability 7. Supports IP trade

  8. Specify-Explore-Refine Methodology Design decisions Model refinement Replacement or re-composition

  9. Y-Chart

  10. Processor behavioral model Language C -> CDFG -> FSMD (FSM +DFG)

  11. Processor structure (Processor-level structural model: NISC) Controller pipelining FU pipelining Datapath pipelining Data forwarding Programmable controller Configurable datapath

  12. Data memory Control inputs Control signals Op1 Op2 RF Op1 Op2 Op3 IR Selector D Q S1 S2 Register Memory D Q Op4 Bus1 Op1 Op2 Next- state logic or Address generator S3 Bus2 D Q Op5 Op6 Output logic or Program memory State register or PC ALU    Op3 Latch Bus3 SR Signal status Register Controller Datapath Processor Control outputs Datapath outputs Processor synthesis Variable binding Operation Binding CA scheduling Bus Binding Component selection Controller Synthesis Processor FSMD model

  13. System behavioral model (Serial-parallel processes: UML + C/ SystemC)

  14. System structure (Netlist of system components: processors, memories, buses)

  15. µProcessor IP Memory Comp. Proc Proc Proc Interface Interface Proc Proc Bus Interface Interface Memory Custom HW System structure System behavior System Synthesis Scheduling Behavior Binding Channel Binding Allocation IF Synthesis Profiling Refinement System

  16. Does it work? • Intuitively it does • Well defined models, rules, transformations, refinements • System level complexity simplified • Worked in the past: layout, logic, RTL? • Proof of concept demonstrated • Embedded System Environment (ESE) • Automatic model generation • Model synthesis and verification • Universal IP: NISC • Productivity gains order of 1000 – 10000 • What is next? • More contributions needed • Change of mind

  17. Conclusions • Extreme makeover is necessary for a new paradigm, where • SW = HW = SOC = Embedded Systems • Simulation based chaos is not acceptable • Design methodology is based on scientific principles • Model algebra is enabling technology for • Embedded system design • System methodology • CAD tools • Design science education • Formalism introduces simplicity that allows • Automatic model generation (No need for languages) • Automatic synthesis and verification (No need for system designers) • Application driven system design (Application experts only needed)

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