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DBBC2

DBBC2. G. Tuccari – INAF Istituto di Radioastronomia. DBBC2 Architecture. IFn (MHz) 1~512, 512~1024,1024~1536, 1536~2048 or 1~1024, 1024~2048 MHz. IF 1abcd. IF 3abcd. IF 4abcd. IF 2abcd. AGC/ Filter. AGC/ Filter. AGC/ Filter. AGC/ Filter. HSI. HSIR. HSI. HSIR. HSI.

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DBBC2

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  1. DBBC2 G. Tuccari – INAF IstitutodiRadioastronomia TOW May 2011

  2. DBBC2 Architecture IFn (MHz) 1~512, 512~1024,1024~1536, 1536~2048 or 1~1024, 1024~2048 MHz IF 1abcd IF 3abcd IF 4abcd IF 2abcd AGC/ Filter AGC/ Filter AGC/ Filter AGC/ Filter HSI HSIR HSI HSIR HSI HSIR ADB 1/2 ADB 1/2 ADB 1/2 FILA OUT ADB 1/2 HSI HSIR VSI 64 ch CORE CORE CORE CORE FILA IN D/A Monitor HSO HSOR HSO HSOR HSO HSOR HSO HSOR PCI PC H-Maser 1024/2048 MHz Synthesizer Distributor PCI Interfaces FS PC TOW May 2011

  3. Reviewof the System Components • AnalogConditioningModule • Analog-DigitalConverter (ADBoard1 - ADBoard2) • Data Processing (CoreBoard2) • Connection and Service (FiLaIN/OUT – FiLa10G) • Timing and Clock (CaT1/2 – Clock and Timing Boards) • Computer Control (PCSet) TOW May 2011

  4. ADBoard1 AnalogtoDigitalConverter Analog input: 0 - 2.2 GHz Max Sampling clock single board: 1.5 GHz Max IstantaneousBandwidth in Real Mode: 750 MHz Max IstantaneousBandwidth in Complex Mode: 1.5 GHz Output Data: 2 x 8-bit @ ¼ SClkDDR TOW May 2011

  5. ADBoard2 AnalogtoDigitalConverter Analog input: 0 – 3.5 GHz Max Sampling clock single board: 2.2 GHz Max IstantaneousBandwidth in Real Mode: 1.1 GHz Max IstantaneousBandwidth in Complex Mode: 2.2 GHz Output Data: 2 x 8-bit @ ¼ SClkDDR 4 x 8-bit @ 1/8 SClk DDR Piggy-back module support for 10-bit output and connection with FiLa10G board. TOW May 2011

  6. Core2 Basic processing unit Input Rate: (4 IFs x 2 bus x 8 bit x SClk/4 DDR) b/s (2 IFs x 4 bus x 8 bit x SClk/8 DDR) b/s More… Typical Output Rate: (64 ch x 32-64-128) Mb/s Programmablearchitecture Es. Digital Down Converter: 1 CoreBoard2 = 4 BBC Max Input/Output Data Rate 32.768 Gbps TOW May 2011

  7. FiLaBoard Connection and Service First and Last board in the stack First: Communication Interface JTAG ProgrammingChannel 1PPS Input Last: 2 VSI Interfaces DA Converter 1PPS Monitor Out 80Hz ContinuousCal Out TOW May 2011

  8. PCSet FPGA device configuration through USB – JTAG interface Communication with 32-bit bus for CoreBoards register setting, total power measurement, statistics of the state, single channel automatic gain control, etc. Communication with Conditioning Modules for IF total power measure, automatic gain control, registers control Field System interface through a network connection TOW May 2011

  9. TOW May 2011

  10. TOW May 2011

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  12. TOW May 2011

  13. DifferentFunctionalitiesAvailable • Digital Down Converter (DDC) • Polyphase Filter Bandpass converter(PFB) • Spectrometers TOW May 2011

  14. General Features • 4 RF/IF Input from 16 (4x4) in a range up to 2.2 (3.5) GHz • Four polarizations or bands available for a single group of 64 output data channel selection (2 VSI output connectors with 1 or 2 Gb/s each) • Output from the stack to FiLa10G ethernet card as 4x2Gbps • 1024/2048 MHz sampling clock frequency • DDC: tunable, channel bandwidth between 1 MHz and 16 MHz, U&L, Continuous cal with 80 Hz synchronization, mode ’astro’, ‘geo’, w-astro’,’ test’ • (on VSI binary counter pattern, next revision added MK5 TVG injection) • PFB: fixed tuning, channel bandwidth 32 MHz, all U or L depending on the Nyquist zone, (next revision VSI test mode injection) • Additional Instrumentation (spectrometers) TOW May 2011

  15. Digital Down Conversionto Base Band ofIndependentChannels A 0101010001001000 010100101010101001 10101011001001010010 001010010100101010101 1010000100101010010110 1001010100000101010100 00010001010101011100100 010101010100001001010010 001010101010101011011100 011010 1100100101 10110010100 101011010010 1010001101010 11010001010010 100101001010111 110100010100111 10 101 1001 10000 100101 010100 0101110 10100100 f A A A 001010101010101010 0101001000100010010 00101010011010010010 010101001001010101000 1101010101010000100100 11010100001001001010000 01011010101010100101010 101001001010010010101010 00100100100 101010010100 0100010101010 1010101000100 11010000001000 00010010100010 100101010010100 0001010010000100 11 011 0100 10100 10100 001000 1110000 10100001 f f f TOW May 2011

  16. PFBConversionto Base Band A 011010 1100100101 10110010100 101011010010 1010001101010 11010001010010 100101001010111 110100010100111 011010 1100100101 10110010100 101011010010 1010001101010 11010001010010 100101001010111 110100010100111 011010 1100100101 10110010100 101011010010 1010001101010 11010001010010 100101001010111 110100010100111 011010 1100100101 10110010100 101011010010 1010001101010 11010001010010 100101001010111 110100010100111 011010 1100100101 10110010100 101011010010 1010001101010 11010001010010 100101001010111 110100010100111 011010 1100100101 10110010100 101011010010 1010001101010 11010001010010 100101001010111 110100010100111 011010 1100100101 10110010100 101011010010 1010001101010 11010001010010 100101001010111 110100010100111 00100100100 101010010100 0100010101010 1010101000100 11010000001000 00010010100010 100101010010100 0001010010000100 f A A A 00100100100 101010010100 0100010101010 1010101000100 11010000001000 00010010100010 100101010010100 0001010010000100 00100100100 101010010100 0100010101010 1010101000100 11010000001000 00010010100010 100101010010100 0001010010000100 00100100100 101010010100 0100010101010 1010101000100 11010000001000 00010010100010 100101010010100 0001010010000100 f f f TOW May 2011

  17. 10G OpticalFiber Ethernet Board FiLa10G Triangle connection between HSI (DBBC fast sampled data bus) – VSI – 10Gb link It can be placed either at the beginning of the chain or at the end - MK5C Piggy-back board for ADB2 TOW May 2011

  18. Connection examples FILA10G MK5C 2xVSI FILA10G MK5C 2xVSI MK5B/B+ MK5B/B • 2 x VSI --> MK5C • 2 x VSI --> MK5C & MK5B TOW May 2011

  19. Connection examples FILA10G 10 Gbps Network 1/2xVSI DBBC FILA10G 2 - 4 -8 - 16Gbps e-VLBI • 2 x VSI --> Network TOW May 2011

  20. FILA10G TOW May 2011

  21. FILA10G and ADB2 TOW May 2011

  22. FILA10G and GLAPPER TOW May 2011

  23. Software • General: c:\DBBC\bin\clock1024.exe (CAT2 1024) c:\DBBC\bin\clock2048.exe (CAT2 2048) c:\DBBC\bin\ad9858.exe (CAT1) c:\DBBC\bin\DBBC client.exe • DDC : c:\DBBC\bin\DBBC Control.exe • c:\DBBC_conf\dbbc_config_file.txt c:\DBBC_conf\FilesDBBC\dbbc2.bit • PFB: c:\DBBC\bin\DBBC poly16 complete.exe • c:\DBBC_conf\dbbc_poly_config_file.txt c:\DBBC_conf\FilesDBBC\poly_dbbc.bit TOW May 2011

  24. Software on socket • DDC : c:\DBBC\bin\DBBC Controlnet.exe (server) c:\DBBC_conf\dbbc_config_file.txt c:\DBBC_conf\FilesDBBC\dbbc2.bit • PFB: c:\DBBC\bin\DBBC Control poly16 net.exe (server) c:\DBBC_conf\dbbc_poly_config_file.txt c:\DBBC_conf\FilesDBBC\poly_dbbc.bit TOW May 2011

  25. In development 512 MHz DDC out tunable 32MHz 1 GHz DDC out tunable 32MHz 1 GHz Parallel Polyphase Filterbank (31ch x 32 MHz) 512 MHz SB (single band 16tr@64MHz 2bit) 1 GHz SB (single band 32tr@64MHz 2bit) Spectrometer 4x512MHz, 32768 total # bin Spectropolarimeter

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