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CS 61C: Great Ideas in Computer Architecture SIMD I

CS 61C: Great Ideas in Computer Architecture SIMD I. Instructor: David A. Patterson http://inst.eecs.Berkeley.edu/~cs61c/sp12. New-School Machine Structures (It’s a bit more complicated!). Software Hardware. Parallel Requests Assigned to computer e.g., Search “Katz”

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CS 61C: Great Ideas in Computer Architecture SIMD I

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  1. CS 61C: Great Ideas in Computer Architecture SIMD I Instructor: David A. Patterson http://inst.eecs.Berkeley.edu/~cs61c/sp12 Spring 2012 -- Lecture #13

  2. New-School Machine Structures(It’s a bit more complicated!) Software Hardware • Parallel Requests Assigned to computer e.g., Search “Katz” • Parallel Threads Assigned to core e.g., Lookup, Ads • Parallel Instructions >1 instruction @ one time e.g., 5 pipelined instructions • Parallel Data >1 data item @ one time e.g., Add of 4 pairs of words • Hardware descriptions All gates @ one time • Programming Languages SmartPhone Warehouse Scale Computer HarnessParallelism & Achieve HighPerformance Computer … Core Core Memory (Cache) Input/Output Core Today’s Lecture Functional Unit(s) Instruction Unit(s) A0+B0 A3+B3 A2+B2 A1+B1 Cache Memory Logic Gates Spring 2012 -- Lecture #13

  3. Review • To access cache, Memory Address divided into 3 fields: Tag, Index, Block Offset • Cache size is Data + Management (tags, valid, dirty bits) • Write misses trickier to implement than reads • Write back vs. Write through • Write allocate vs. No write allocate • Cache Performance Equations: • CPU time = IC × CPIstall × CC = IC × (CPIideal + Memory-stall cycles) × CC • AMAT = Time for a hit + Miss rate x Miss penalty • If understand caches, can adapt software to improve cache performance and thus program performance Spring 2012 -- Lecture #13

  4. Agenda • Flynn Taxonomy • Administrivia • DLP and SIMD • Intel Streaming SIMD Extensions (SSE) • (Amdahl’s Law if time permits) Spring 2012 -- Lecture #13

  5. Alternative Kinds of Parallelism:The Programming Viewpoint • Job-level parallelism/process-level parallelism • Running independent programs on multiple processors simultaneously • Example? • Parallel processing program • Single program that runs on multiple processors simultaneously • Example? Spring 2012 -- Lecture #13

  6. Alternative Kinds of Parallelism:Single Instruction/Single Data Stream • Single Instruction, Single Data stream (SISD) • Sequential computer that exploits no parallelism in either the instruction or data streams. Examples of SISD architecture are traditional uniprocessor machines Processing Unit Spring 2012 -- Lecture #13

  7. Alternative Kinds of Parallelism:Multiple Instruction/Single Data Stream • Multiple Instruction, Single Data streams (MISD) • Computer that exploits multiple instruction streams against a single data stream for data operations that can be naturally parallelized. For example, certain kinds of array processors. • No longer commonly encountered, mainly of historical interest only Spring 2012 -- Lecture #13

  8. Alternative Kinds of Parallelism:Single Instruction/Multiple Data Stream • Single Instruction, Multiple Data streams (SIMD or “sim-dee”) • Computer that exploits multiple data streams against a single instruction stream to operations that may be naturally parallelized, e.g.,Intel SIMD instruction extensions or NVIDIA Graphics Processing Unit (GPU) Spring 2012 -- Lecture #13

  9. Alternative Kinds of Parallelism:Multiple Instruction/Multiple Data Streams • Multiple Instruction, Multiple Data streams (MIMD or “mim-dee”) • Multiple autonomous processors simultaneously executing different instructions on different data. • MIMD architectures include multicore and Warehouse Scale Computers • (Discuss after midterm) Spring 2012 -- Lecture #13

  10. Flynn Taxonomy • In 2012, SIMD and MIMD most common parallel computers • Most common parallel processing programming style: Single Program Multiple Data (“SPMD”) • Single program that runs on all processors of an MIMD • Cross-processor execution coordination through conditional expressions (thread parallelism after midterm ) • SIMD (aka hw-level data parallelism): specialized function units, for handling lock-step calculations involving arrays • Scientific computing, signal processing, multimedia (audio/video processing) Spring 2012 -- Lecture #13

  11. Data-Level Parallelism (DLP) (from 2nd lecture, January 19) • 2 kinds of DLP • Lots of data in memory that can be operated on in parallel (e.g., adding together 2 arrays) • Lots of data on many disks that can be operated on in parallel (e.g., searching for documents) • 2nd lecture (and 1st project) did DLP across 10s of servers and disks using MapReduce • Today’s lecture (and 3rd project) does Data Level Parallelism (DLP) in memory Spring 2012 -- Lecture #13

  12. SIMD Architectures • Data parallelism: executing one operation on multiple data streams • Example to provide context: • Multiplying a coefficient vector by a data vector (e.g., in filtering) y[i] := c[i] x[i], 0 i < n • Sources of performance improvement: • One instruction is fetched & decoded for entire operation • Multiplications are known to be independent • Pipelining/concurrency in memory access as well Spring 2012 -- Lecture #13

  13. “Advanced Digital Media Boost” • To improve performance, Intel’s SIMD instructions • Fetch one instruction, do the work of multiple instructions • MMX (MultiMediaeXtension, Pentium II processor family) • SSE (Streaming SIMD Extension, Pentium III and beyond) Spring 2012 -- Lecture #13

  14. Example: SIMD Array Processing for each f in array f = sqrt(f) for each f in array { load f to the floating-point register calculate the square root write the result from the register to memory } for each 4 members in array { load 4 members to the SSE register calculate 4 square roots in one operation store the 4 results from the register to memory } SIMD style Spring 2012 -- Lecture #13

  15. Intel SSE Instruction Categoriesfor Multimedia Support • SSE-2+ supports wider data types to allow 16 x 8-bit and 8 x 16-bit operands Spring 2012 -- Lecture #13

  16. Intel Architecture SSE2+128-Bit SIMD Data Types • Note: in Intel Architecture (unlike MIPS) a word is 16 bits • Single precision FP: Double word (32 bits) • Double precision FP: Quad word (64 bits) 16 / 128 bits 122 121 96 95 80 79 64 63 48 47 32 31 16 15 8 / 128 bits 122 121 96 95 80 79 64 63 48 47 32 31 16 15 96 95 64 63 32 31 4 / 128 bits 64 63 2 / 128 bits Spring 2012 -- Lecture #13

  17. Administrivia • Lab #7 posted • Midterm in 1 week: • Exam: Tu, Mar 6, 6:40-9:40 PM, 2050 VLSB • Covers everything through lecture today • Closed book, can bring one sheet notes, both sides • Copy of Green card will be supplied • No phones, calculators, …; just bring pencils & eraser • TA Review: Su, Mar 4, Starting 2PM, 2050 VLSB • Will send (anonymous) 61C midway survey before Midterm Spring 2012 -- Lecture #13

  18. Project 2, Part 2 Grades • On-time submissions grades • Majority got perfect or near-perfect scores • Median 81.5, Mean 74.1 Spring 2012 -- Lecture #13

  19. Most Common Test Failures Proj 2 Spring 2012 -- Lecture #13

  20. 61C in the News “The smartphone market last year was a half billion units,” [Timothy D. Cook, the Apple chief executive] continued. “In 2015, it is projected to be a billion units. When you take it in the context of these numbers, the truth is, this is a jaw-dropping industry.” … “I think currently the biggest trend is not the price, but the capability,”Shao Yang [marketing director for mobile devices at Huawei] said. “There is a competition in capability. The function of the phone will change very fast.” “Apple’s Lead in Smartphones Is Not Guaranteed,” By Kevin O’Brien, New York Times, February 27, 2012 Spring 2012 -- Lecture #11

  21. Agenda • Flynn Taxonomy • Administrivia • DLP and SIMD • Technology Break • Intel Streaming SIMD Extensions (SSE) • (Amdahl’s Law if time permits) Spring 2012 -- Lecture #13

  22. XMM Registers • Architecture extended with eight 128-bit data registers: XMM registers • IA 64-bit address architecture: available as 16 64-bit registers (XMM8 – XMM15) • E.g., 128-bit packed single-precision floating-point data type (doublewords), allows four single-precision operations to be performed simultaneously Spring 2012 -- Lecture #13

  23. SSE/SSE2 Floating Point Instructions Move does both load and store xmm: one operand is a 128-bit SSE2 register mem/xmm: other operand is in memory or an SSE2 register {SS} Scalar Single precision FP: one 32-bit operand in a 128-bit register {PS} Packed Single precision FP: four 32-bit operands in a 128-bit register {SD} Scalar Double precision FP: one 64-bit operand in a 128-bit register {PD} Packed Double precision FP, or two 64-bit operands in a 128-bit register {A} 128-bit operand is aligned in memory {U} means the 128-bit operand is unaligned in memory {H} means move the high half of the 128-bit operand {L} means move the low half of the 128-bit operand Spring 2012 -- Lecture #13

  24. Example: Add Two Single PrecisionFP Vectors Computation to be performed: vec_res.x = v1.x + v2.x; vec_res.y = v1.y + v2.y; vec_res.z = v1.z + v2.z; vec_res.w = v1.w + v2.w; SSE Instruction Sequence: (Note: Destination on the right in x86 assembly) movaps address-of-v1, %xmm0 // v1.w | v1.z | v1.y | v1.x -> xmm0 addps address-of-v2, %xmm0 // v1.w+v2.w | v1.z+v2.z | v1.y+v2.y | v1.x+v2.x -> xmm0 movaps %xmm0, address-of-vec_res mov a ps : move from mem to XMM register,memory aligned, packed single precision add ps : add from mem to XMM register,packed single precision mov a ps : move from XMM register to mem, memory aligned, packed single precision Spring 2012 -- Lecture #13

  25. Packed and Scalar Double-Precision Floating-Point Operations Spring 2012 -- Lecture #13

  26. Example: Image Converter • Converts BMP (bitmap) image to a YUV (color space) image format: • Read individual pixels from the BMP image, convert pixels into YUV format • Can pack the pixels and operate on a set of pixels with a single instruction • E.g., bitmap image consists of 8 bit monochrome pixels • Pack these pixel values in a 128 bit register (8 bit * 16 pixels), can operate on 16 values at a time • Significant performance boost Spring 2012 -- Lecture #13

  27. Example: Image Converter • FMADDPS – Multiply and add packed single precision floating point instruction • One of the typical operations computed in transformations (e.g., DFT of FFT) N P = ∑f(n) × x(n) n = 1 Spring 2012 -- Lecture #13

  28. Example: Image Converter Floating point numbers f(n) and x(n) in src1 and src2; p in dest; C implementation for N = 4 (128 bits): for (int i =0; i< 4; i++) p = p + src1[i] * src2[i]; Regular x86 instructions for the inner loop: //src1 is on the top of the stack; src1 * src2 -> src1 fmul DWORD PTR _src2$[%esp+148] //p = ST(1), src1 = ST(0); ST(0)+ST(1) -> ST(1); ST-Stack Top faddp %ST(0), %ST(1) (Note: Destination on the right in x86 assembly) Number regular x86 Fl. Pt. instructions executed: 4 * 2 = 8 Spring 2012 -- Lecture #13

  29. Example: SSE Image Converter Floating point numbers f(n) and x(n) in src1 and src2; p in dest;C implementation for N = 4 (128 bits): for (int i =0; i< 4; i++) p = p + src1[i] * src2[i]; • SSE2 instructions for the inner loop: //xmm0 = p, xmm1 = src1[i], xmm2 = src2[i] mulps %xmm1, %xmm2 // xmm2 * xmm1 -> xmm2 addps %xmm2, %xmm0 // xmm0 + xmm2 -> xmm0 • Number regular instructions executed: 2 SSE2 instructions vs. 8 x86 • SSE5 instruction accomplishes same in one instruction: fmaddps %xmm0, %xmm1, %xmm2, %xmm0 // xmm2 * xmm1 + xmm0 -> xmm0 // multiply xmm1 x xmm2 paired single, // then add product paired single to sum in xmm0 • Number regular instructions executed: 1 SSE5 instruction vs. 8 x86 Spring 2012 -- Lecture #13

  30. Intel SSE Intrinsics • Intrinsics are C functions and procedures for putting in assembly language, including SSE instructions • With intrinsics, can program using these instructions indirectly • One-to-one correspondence between SSE instructions and intrinsics Spring 2012 -- Lecture #13

  31. Example SSE Intrinsics Instrinsics: Corresponding SSE instructions: • Vector data type: _m128d • Load and store operations: _mm_load_pd MOVAPD/aligned, packed double _mm_store_pd MOVAPD/aligned, packed double _mm_loadu_pd MOVUPD/unaligned, packed double _mm_storeu_pd MOVUPD/unaligned, packed double • Load and broadcast across vector _mm_load1_pd MOVSD + shuffling/duplicating • Arithmetic: _mm_add_pd ADDPD/add, packed double _mm_mul_pd MULPD/multiple, packed double 02/09/2010 CS267 Lecture 7 31 Spring 2012 -- Lecture #13

  32. Example: 2 x 2 Matrix Multiply Definition of Matrix Multiply: A1,1 A1,2 B1,1 B1,2 C1,1=A1,1B1,1 + A1,2B2,1 C1,2=A1,1B1,2+A1,2B2,2 2 x = Ci,j = (A×B)i,j = ∑Ai,k× Bk,j A2,1 A2,2 B2,1 B2,2 C2,1=A2,1B1,1 + A2,2B2,1 C2,2=A2,1B1,2+A2,2B2,2 k = 1 Spring 2012 -- Lecture #13

  33. Example: 2 x 2 Matrix Multiply • Using the XMM registers • 64-bit/double precision/two doubles per XMM reg C1 C1,1 C2,1 Stored in memory in Column order C2 C1,2 C2,2 A A1,i A2,i B1 Bi,1 Bi,1 B2 Bi,2 Bi,2 Spring 2012 -- Lecture #13

  34. Example: 2 x 2 Matrix Multiply • Initialization • I = 1 C1 0 0 C2 0 0 _mm_load_pd: Stored in memory in Column order A A1,1 A2,1 _mm_load1_pd: SSE instruction that loads a double word and stores it in the high and low double words of the XMM register B1 B1,1 B1,1 B2 B1,2 B1,2 Spring 2012 -- Lecture #13

  35. Example: 2 x 2 Matrix Multiply • Initialization • I = 1 C1 0 0 C2 0 0 _mm_load_pd: Load 2 doubles into XMM reg, Stored in memory in Column order A A1,1 A2,1 _mm_load1_pd: SSE instruction that loads a double word and stores it in the high and low double words of the XMM register (duplicates value in both halves of XMM) B1 B1,1 B1,1 B2 B1,2 B1,2 Spring 2012 -- Lecture #13

  36. Example: 2 x 2 Matrix Multiply • First iteration intermediate result • I = 1 C1 0+A1,1B1,1 0+A2,1B1,1 c1 = _mm_add_pd(c1,_mm_mul_pd(a,b1)); c2 = _mm_add_pd(c2,_mm_mul_pd(a,b2)); SSE instructions first do parallel multiplies and then parallel adds in XMM registers C2 0+A1,1B1,2 0+A2,1B1,2 _mm_load_pd: Stored in memory in Column order A A1,1 A2,1 _mm_load1_pd: SSE instruction that loads a double word and stores it in the high and low double words of the XMM register (duplicates value in both halves of XMM) B1 B1,1 B1,1 B2 B1,2 B1,2 Spring 2012 -- Lecture #13

  37. Example: 2 x 2 Matrix Multiply • First iteration intermediate result • I = 2 C1 0+A1,1B1,1 0+A2,1B1,1 c1 = _mm_add_pd(c1,_mm_mul_pd(a,b1)); c2 = _mm_add_pd(c2,_mm_mul_pd(a,b2)); SSE instructions first do parallel multiplies and then parallel adds in XMM registers C2 0+A1,1B1,2 0+A2,1B1,2 _mm_load_pd: Stored in memory in Column order A A1,2 A2,2 _mm_load1_pd: SSE instruction that loads a double word and stores it in the high and low double words of the XMM register (duplicates value in both halves of XMM) B1 B2,1 B2,1 B2 B2,2 B2,2 Spring 2012 -- Lecture #13

  38. Example: 2 x 2 Matrix Multiply • Second iteration intermediate result • I = 2 C2,1 C1,1 C1 A1,1B1,1+A1,2B2,1 A2,1B1,1+A2,2B2,1 c1 = _mm_add_pd(c1,_mm_mul_pd(a,b1)); c2 = _mm_add_pd(c2,_mm_mul_pd(a,b2)); SSE instructions first do parallel multiplies and then parallel adds in XMM registers C2 A1,1B1,2+A1,2B2,2 A2,1B1,2+A2,2B2,2 C2,2 C1,2 _mm_load_pd: Stored in memory in Column order A A1,2 A2,2 _mm_load1_pd: SSE instruction that loads a double word and stores it in the high and low double words of the XMM register (duplicates value in both halves of XMM) B1 B2,1 B2,1 B2 B2,2 B2,2 Spring 2012 -- Lecture #13

  39. Live Example: 2 x 2 Matrix Multiply Definition of Matrix Multiply: A1,1 1 A1,2 0 1 B1,1 B1,2 3 C1,1= 1*1+ 0*2 = 1 C1,1=A1,1B1,1 + A1,2B2,1 C1,2= 1*3 + 0*4 = 3 C1,2=A1,1B1,2+A1,2B2,2 x x = = 2 Ci,j = (A×B)i,j = ∑Ai,k× Bk,j A2,1 0 A2,2 1 2 B2,1 B2,2 4 C2,1= 0*1 + 1*2 = 2 C2,1=A2,1B1,1 + A2,2B2,1 C2,2=A2,1B1,2+A2,2B2,2 C2,2= 0*3 + 1*4 = 4 k = 1 Spring 2012 -- Lecture #13

  40. Example: 2 x 2 Matrix Multiply(Part 1 of 2) #include <stdio.h> // header file for SSE compiler intrinsics #include <emmintrin.h> // NOTE: vector registers will be represented in comments as v1 = [ a | b] // where v1 is a variable of type __m128d anda, b are doubles intmain(void) { // allocate A,B,C aligned on 16-byte boundaries double A[4] __attribute__ ((aligned (16))); double B[4] __attribute__ ((aligned (16))); double C[4] __attribute__ ((aligned (16))); intlda = 2; inti = 0; // declare several 128-bit vector variables __m128d c1,c2,a,b1,b2; // Initialize A, B, C for example /* A = (note column order!) 1 0 0 1 */ A[0] = 1.0; A[1] = 0.0; A[2] = 0.0; A[3] = 1.0; /* B = (note column order!) 1 3 2 4 */ B[0] = 1.0; B[1] = 2.0; B[2] = 3.0; B[3] = 4.0; /* C = (note column order!) 0 0 0 0 */ C[0] = 0.0; C[1] = 0.0; C[2] = 0.0; C[3] = 0.0; Spring 2012 -- Lecture #13

  41. Example: 2 x 2 Matrix Multiply(Part 2 of 2) // used aligned loads to set // c1 = [c_11 | c_21] c1 = _mm_load_pd(C+0*lda); // c2 = [c_12 | c_22] c2 = _mm_load_pd(C+1*lda); for (i = 0; i < 2; i++) { /* a = i = 0: [a_11 | a_21] i = 1: [a_12 | a_22] */ a = _mm_load_pd(A+i*lda); /* b1 = i = 0: [b_11 | b_11] i = 1: [b_21 | b_21] */ b1 = _mm_load1_pd(B+i+0*lda); /* b2 = i = 0: [b_12 | b_12] i = 1: [b_22 | b_22] */ b2 = _mm_load1_pd(B+i+1*lda); /* c1 = i = 0: [c_11 + a_11*b_11 | c_21 + a_21*b_11] i = 1: [c_11 + a_21*b_21 | c_21 + a_22*b_21] */ c1 = _mm_add_pd(c1,_mm_mul_pd(a,b1)); /* c2 = i = 0: [c_12 + a_11*b_12 | c_22 + a_21*b_12] i = 1: [c_12 + a_21*b_22 | c_22 + a_22*b_22] */ c2 = _mm_add_pd(c2,_mm_mul_pd(a,b2)); } // store c1,c2 back into C for completion _mm_store_pd(C+0*lda,c1); _mm_store_pd(C+1*lda,c2); // print C printf("%g,%g\n%g,%g\n",C[0],C[2],C[1],C[3]); return 0; } Spring 2012 -- Lecture #13

  42. Inner loop from gcc –O -S L2: movapd (%rax,%rsi), %xmm1 //Load aligned A[i,i+1]->m1 movddup (%rdx), %xmm0 //Load B[j], duplicate->m0 mulpd %xmm1, %xmm0 //Multiply m0*m1->m0 addpd %xmm0, %xmm3 //Add m0+m3->m3 movddup 16(%rdx), %xmm0 //Load B[j+1], duplicate->m0 mulpd %xmm0, %xmm1 //Multiply m0*m1->m1 addpd %xmm1, %xmm2 //Add m1+m2->m2 addq $16, %rax // rax+16 -> rax (i+=2) addq $8, %rdx // rdx+8 -> rdx (j+=1) cmpq $32, %rax // rax == 32? jne L2 // jump to L2 if not equal movapd %xmm3, (%rcx) //store aligned m3 into C[k,k+1] movapd %xmm2, (%rdi) //store aligned m2 into C[l,l+1] Spring 2012 -- Lecture #13

  43. Performance-Driven ISA Extensions • Subword parallelism, used primarily for multimedia applications • Intel MMX: multimedia extension • 64-bit registers can hold multiple integer operands • Intel SSE: Streaming SIMD extension • 128-bit registers can hold several floating-point operands • Adding instructions that do more work per cycle • Shift-add: replace two instructions with one (e.g., multiply by 5) • Multiply-add: replace two instructions with one (x := c + a b) • Multiply-accumulate: reduce round-off error (s := s + a b) • Conditional copy: to avoid some branches (e.g., in if-then-else) Spring 2012 -- Lecture #13

  44. Exec time w/o E Speedup w/ E = ---------------------- Exec time w/ E Big Idea: Amdahl’s (Heartbreaking) Law • Speedup due to enhancement E is • Suppose that enhancement E accelerates a fraction F (F <1) of the task by a factor S (S>1) and the remainder of the task is unaffected Execution Time w/o E  [ (1-F) + F/S] Execution Time w/ E = 1 / [ (1-F) + F/S ] Speedup w/ E = Spring 2012 -- Lecture #13

  45. Big Idea: Amdahl’s Law Speedup = Example: the execution time of half of the program can be accelerated by a factor of 2.What is the program speed-up overall? Spring 2012 -- Lecture #13

  46. Big Idea: Amdahl’s Law Speedup = 1 Example: the execution time of half of the program can be accelerated by a factor of 2.What is the program speed-up overall? (1 - F) + F S Non-speed-up part Speed-up part 1 1 = = 1.33 0.5 + 0.5 0.5 + 0.25 2 Spring 2012 -- Lecture #13

  47. Big Idea: Amdahl’s Law If the portion ofthe program thatcan be parallelizedis small, then thespeedup is limited The non-parallelportion limitsthe performance Spring 2012 -- Lecture #13

  48. Example #1: Amdahl’s Law Speedup w/ E = 1 / [ (1-F) + F/S ] • Consider an enhancement which runs 20 times faster but which is only usable 25% of the time Speedup w/ E = 1/(.75 + .25/20) = 1.31 • What if its usable only 15% of the time? Speedup w/ E = 1/(.85 + .15/20) = 1.17 • Amdahl’s Law tells us that to achieve linear speedup with 100 processors, none of the original computation can be scalar! • To get a speedup of 90 from 100 processors, the percentage of the original program that could be scalar would have to be 0.1% or less Speedup w/ E = 1/(.001 + .999/100) = 90.99 Spring 2012 -- Lecture #13

  49. Example #2: Amdahl’s Law Speedup w/ E = 1 / [ (1-F) + F/S ] • Consider summing 10 scalar variables and two 10 by 10 matrices (matrix sum) on 10 processors Speedup w/ E = 1/(.091 + .909/10) = 1/0.1819 = 5.5 • What if there are 100 processors ? Speedup w/ E = 1/(.091 + .909/100) = 1/0.10009 = 10.0 • What if the matrices are 100 by 100 (or 10,010 adds in total) on 10 processors? Speedup w/ E = 1/(.001 + .999/10) = 1/0.1009 = 9.9 • What if there are 100 processors ? Speedup w/ E = 1/(.001 + .999/100) = 1/0.01099 = 91 Spring 2012 -- Lecture #13

  50. Strong and Weak Scaling • To get good speedup on a multiprocessor while keeping the problem size fixed is harder than getting good speedup by increasing the size of the problem. • Strong scaling: when speedup can be achieved on a parallel processor without increasing the size of the problem • Weak scaling: when speedup is achieved on a parallel processor by increasing the size of the problem proportionally to the increase in the number of processors • Load balancing is another important factor: every processor doing same amount of work • Just 1 unit with twice the load of others cuts speedup almost in half Spring 2012 -- Lecture #13

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