Embedded System Platform: an Example

1. Embedded System Platform: an Example Leiden Embedded Research Group LIACS, Leiden University The Netherlands

2. Generic Embedded System Platform memory memory memory RPU IPcore CPU … BUS I/O device I/O device memory memory … …

3. CPU + Memory (von Neumann architecture) 0 Memory Data + Program CPU 1 PC 2 address IR 1. PC := 200 2. Fetch => IR := Mem[PC] 3. Decode IR 4. Execute 5. PC := PC + 1 6. goto 2 data 200 ADD a1,a2,aN GPR N

4. CPU + Memory (Harvard architecture) address CPU Program Memory PC data IR address Data Memory data GPR

5. Memory Device Organization Memory array Data Width: w Addres Width: n Size: 2n cells n rowAddr Type of Memory: - RAM, ROM - SRAM, DRAM - … columnAddr w

6. Typical generic SRAM SRAM - Very Fast - High Area - Low Capacity - … CE’ R/W’ Adrs Data

7. Generic SRAM timing CE’ R/W’ Adrs From SRAM From CPU Data read write time

8. Generic DRAM device CE’ DRAM - Slower than SRAM - Low Area - High Capacity - Refresh is needed - … R/W’ RAS’ CAS’ Adrs Data

9. Generic DRAM timing CE’ R/W’ RAS’ CAS’ row adrs col adrs Adrs Data data time

10. Memory Map Memory Map Local Mem 0 I/O device 1 2 3 I/O device 2 5 CPU : I/O device1 50 Mem 1 100 BUS : 200 I/O deviceN Local Mem Mem1 N

11. CPU + Generic I/O Device SLAVE MASTER Status Regs CPU data/address mechanism Control Regs Data Regs Busy-Wait Interface

12. CPU + Generic I/O Device SLAVE MASTER intr request Status Regs CPU data/address mechanism Control Regs intr ack Data Regs Interrupt Interface

13. Communication with many I/Os interrupt acknowledge device 1 device 2 device n interrupt requests CPU L1 L2 .. Ln

14. Generic bus structure m • Address: • Data: • Control: n c

15. Fixed-delay memory access read = 1 adrs = A R/W W R/W data mem[adrs] = data R adrs data = mem[adrs] reg = data memory CPU

16. Variable-delay memory access read = 1 adrs = A R/W done = 0 mem[adrs] = data done = 1 data W R/W R n adrs done data = mem[adrs] done = 1 y done memory reg = data CPU

17. Typical bus access (protocol) clock R/W’ Address enable adrs Data Ready’ data write read time

18. Multiple Master-Slave memory memory memory RPU IPcore CPU … Arbiter BUS I/O device I/O device memory memory … …

19. Bus Bridges memory memory memory RPU IPcore CPU BUS3 Bridge1 BUS2 BUS1 Bridge3 I/O device I/O device Bridge2 BUS3 memory memory …

20. Internal Structure of an RPU

21. IP Core (Soft or Hardwired) Memory Interface Bus Interface

22. LERC Lab: AlphaData Board Pro 2VP7 / 2VP20 FF1152

23. Target Platform Data PCI bus Select Host Interface Data Address Data Control Microprocessor Address Multiplexer Control Control Memory Banks Status Pentium IV Control Data Address HW Design Data Virtex-II Pro 2VP20 FPGA ADM-XRCII board

24. HW Design Block

25. MicroBlaze Core Block Diagram

26. LMB Write Operation

27. LMB Read operation

28. Your homework • Group A: What is a PCI (Peripheral Component Interconnect) bus? What is its structure? How does it operate? Study the PCI Interface PLX 9656 chip. • Group B: What is an FPGA (Field Programmable Gate Array) chip? What is its structure? How does it operate? Study the Virtex-II Pro 2VP20 chip. • Group C: What is a ZBT (Zero Bus Turnaround) SRAM memory? What is its structure? How does it operate? Study the MT55L256L36P chip. Pro 2VP7 / 2VP20 FF1152