1. UsefulModelingTechniques Programmable Logic Design (40-493) Fall 2001 Computer Engineering Department Sharif University of Technology Maziar Gudarzi

2. Outline • Procedural Continuous Assignment • Overriding Parameters • Conditional Compilation and Execution • Useful System Tasks

3. Procedural Continuous Assignment Useful Modeling Techniques

4. Procedural Continuous Assignment • Overrides, for a certain time, the effect of regular assignments to a variable. • Two types • assign/deassign • Works only on register data types • force/release • Works on both register and net data types

5. Procedural Continuous Assignment (cont’d) • assign/deassign • Keywords • assign: overrides regular procedural assignments • deassign: re-enables regular procedural assignments • After deassign: • Last value remains on the register until a new procedural assignment changes it.

6. Procedural Continuous Assignment (cont’d) • force/release • Keywords: • force: overrides all procedural/continuous/ procedural continuous assignments • release: re-enables other assignments • Hence, assignments in priority order: 1. force 2. assign (procedural continuous) 3. Procedural/continuous assignments

7. Overriding Parameters Useful Modeling Techniques

8. Overriding Parameters • Two methods • defparam statement • Module instance parameter values • defparam statement • Keyword: defparam • Syntax: defparam <parameter_hierarchical_name>=<value>;

9. Overriding Parameters (cont’d) • Module instance parameter values • Parameters are overridden when the module is instantiated • Syntax: <module_name> #(<param_vals>) <instance_name>;

10. Conditional Compilation and Execution Useful Modeling Techniques

11. Conditional Compilation • Usage: • To compile some part of code under certain conditions • Keywords: • ‘ifdef, `else, `endif

12. Conditional Execution • Usage: • To execute some part of code when a flag is set at runtime • Used only in behavioral modeling • Not contained in Verilog IEEE Standard, • Keywords: • $test$plusargs • Syntax: • $test$plusargs( <argument_to_check> )

13. UsefulSystem Tasks Useful Modeling Techniques

14. Useful System TasksFile Output • Opening a file • Syntax: <file_handle> = $fopen( “<file_name>” ); • File_handle is a 32 bit value, called multi-channel descriptor • Only 1 bit is set in each descriptor • Standard output has a descriptor of 1 (Channel 0)

15. Useful System TasksFile Output (cont’d) • Writing to files • $fdisplay, $fmonitor, $fwrite, $fstrobe • Syntax: $fdisplay(<handle>, p1, p2,…, pn); • Closing files • $fclose(<handle>);

16. Useful System TasksRandom Number Generation • Syntax: $random; $random(<seed>); • Returns a 32 bit random value

17. Useful System TasksInitializing Memory from File • Keywords: • $readmemb, $readmemh • Syntax: $readmemb(“<file_name>”, <memory_name>); $readmemb(“<file_name>”, <memory_name>, <start_addr>); $readmemb(“<file_name>”, <memory_name>, <start_addr>,<finish_addr>);

18. Useful System TasksValue Change Dump (VCD) File • ASCII file containing information on • Simulation time • Scope and signal definitions • Signal value changes • Keywords • $dumpvars • $dumpfile • $dumpon • $dumpoff • $dumpall

19. Today Summary • Reviewed some modeling techniques useful in various applications.

20. Complementary Notes • Assignment 7 (Optional, Extra Score) • Chapter 9: • All exercises with ModelSim, except for 3 and 5 • 3 and 5 in paper and pencil • Due date: Saturday, Day 22nd • Lab. Final Project • Announce your group members and tart your work

21. Complementary Notes (cont’d) • Don’t forget to subscribe to course mailing list: ce493list