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Los tOHMales CalI e ntes

Los tOHMales CalI e ntes. Lauren Cash, Chuhong Duan Rebecca Reed, Andrew Tyler. ECE 4332: Intro to VLSI. Introduction. ECE 4332: Intro to VLSI. Project: Design a high-speed 64KB SRAM cache Make optimizations that influence p ower c onsumption, area and total delay Metric:

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Los tOHMales CalI e ntes

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  1. Los tOHMalesCalIentes Lauren Cash, ChuhongDuan Rebecca Reed, Andrew Tyler ECE 4332: Intro to VLSI

  2. Introduction ECE 4332: Intro to VLSI

  3. Project: • Design a high-speed 64KB SRAM cache • Make optimizations that influence power consumption, area and total delay • Metric: Delay^2*access-energy*idle-power*area ECE 4332: Intro to VLSI

  4. Overview ECE 4332: Intro to VLSI

  5. ECE 4332: Intro to VLSI

  6. Sized standard 6T Bit Cell • Row decoder: predecode stage (4-16) • Column deMUX: precode stage (3-8, 2-4) • PreCharge/BL/BLB • High Speed Sense Amp • Column MUX for output data Components Figure : Simple SRAM 6T Bit Cell (U.Va ECE wiki) Figure : Hierarchical decoders ECE 4332: Intro to VLSI

  7. The Simulations ECE 4332: Intro to VLSI

  8. Simulations ECE 4332: Intro to VLSI

  9. Process Corners - FF ECE 4332: Intro to VLSI

  10. Process Corners - FS ECE 4332: Intro to VLSI

  11. Process Corners - SF ECE 4332: Intro to VLSI

  12. Process Corners - SS ECE 4332: Intro to VLSI

  13. Layout ECE 4332: Intro to VLSI

  14. Single Bit cell Figure : Los tOHMalesCalientes, Bit Cell Layout ECE 4332: Intro to VLSI

  15. High Speed Sense Amp Figure : Los tOHMalesCalientes, Bit Cell Layout ECE 4332: Intro to VLSI

  16. Pre-charge Layout Figure : Los tOHMalesCalientes, Pre-charge Layout ECE 4332: Intro to VLSI

  17. 32x1 Mux Figure : Los tOHMalesCalientes, 32x1 Mux ECE 4332: Intro to VLSI

  18. Pre-Decoder Figure : Los tOHMalesCalientes, Pre-Decoder Layout ECE 4332: Intro to VLSI

  19. Row Decoder Figure : Los tOHMalesCalientes, Row Decoder ECE 4332: Intro to VLSI

  20. Full Layout Figure : Los tOHMalesCalientes, Full Layout ECE 4332: Intro to VLSI

  21. Optimizations ECE 4332: Intro to VLSI

  22. High speed Sense Amp architecture • BL/BLB/PRECH Logic • Pre-decoder logic • Decoder location • Square cache architecture • Write drive size ECE 4332: Intro to VLSI

  23. High Speed Sense Amp • Speeded up ~50% Figure. High Speed Sense Amp for Cache Application (Hsu, Ho, (2004)) ECE 4332: Intro to VLSI

  24. Write Driver Size Figure. Write delay vs. BL driver size ECE 4332: Intro to VLSI

  25. Metrics ECE 4332: Intro to VLSI

  26. ECE 4332: Intro to VLSI

  27. ECE 4332: Intro to VLSI

  28. References Hsu, C.-L., & Ho, M.-H. (2004). High-speed sense amplifier for SRAM applications. The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings (Vol. 1, pp. 577 – 580 vol.1). Presented at the The 2004 IEEE Asia-Pacific Conference on Circuits and Systems, 2004. Proceedings. doi:10.1109/APCCAS.2004.1412828 ECE 4332: Intro to VLSI

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