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Exploring Advanced Parallel Processing Techniques: HPS and Data Flow Models

This article delves into advanced parallel processing techniques, focusing on the High-Performance Computing (HPS) paradigm and data flow models. We explore concepts like pipelining, SIMD, and VLIW, highlighting their impact on speed and efficiency in computation. Through an example of vector processing, we contrast scalar and vector code performance, showcasing the benefits of vectorization techniques. Additionally, we discuss the principles of data-driven execution, illustrating how dependencies dictate processing without a traditional program counter, leading to more asynchronous operations.

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Exploring Advanced Parallel Processing Techniques: HPS and Data Flow Models

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Presentation Transcript

  1. Single Thread Parallelism

  2. Outline • Pipelining • SIMD (both vector and array processing) • VLIW • DAE • HPS • Data Flow

  3. An example: Vector processing • The scalar code: for i=1,50 A(i) = (B(i)+C(i))/2; • The vector code: lvs 1 lvl 50 vld V0,B vld V1,C vadd V2,V0,V1 vshf V3,V2,1 vst V3,A

  4. Vector processing example (continued) • Scalar code (loads take 11 clock cycles): • Vector code (no vector chaining): • Vector code (with chaining): • Vector code (with 2 load, 1 store port to memory):

  5. The HPS Paradigm • Incorporated the following: • Aggressive branch prediction • Speculative execution • Wide issue • Out-of-order execution • In-order retirement • First published in Micro-18 (1985) • Patt, Hwu, Shebanow: Introduction to HPS • Patt, Melvin, Hwu, Shebanow: Critical issues

  6. Data Flow • Data Driven execution of inst-level Graphical code • Nodes are operators • Arcs are I/O • Only REAL dependencies constrain processing • Anti-dependencies don’t (write-after-read) • Output dependencies don’t (write-after-write) • NO sequential I-stream (No program counter) • Operations execute ASYNCHRONOUSLY • Instructions do not reference memory • (at least memory as we understand it) • Execution is triggered by presence of data

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