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Microcomputer Systems 1

Microcomputer Systems 1. Interaction of ADSP-BF533 Ez-Kit Lite with the outside world LAB2 Example. BF533 EZ-Kit Lite. The EZ-KIT Lite provides four (4) push buttons and six (6) LEDs for general-purpose IO. 4 SW push-button switches

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Microcomputer Systems 1

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  1. Microcomputer Systems 1 Interaction of ADSP-BF533 Ez-Kit Lite with the outside world LAB2 Example

  2. BF533 EZ-Kit Lite • The EZ-KIT Lite provides • four (4) push buttons and • six (6) LEDs for general-purpose IO. • 4 SW push-button switches • The four general-purpose push button switches are labeled SW4 through SW7. A status of each individual button can be read through programmable flag (PF) inputs: • PF8 through PF11. • A PF reads 1 when a corresponding switch is being pressed-on. When the switch is released, the PF reads 0. • A connection between the push button and PF input is established through the SW9 DIP switch. • 6 LEDs • The six LEDs, labeled LED4 through LED9, are accessed via some of the general-purpose IO pins of the flash memory interface. Veton Këpuska

  3. BF533 EZ-Kit Lite Veton Këpuska

  4. SW9 Switch For more information see “ADSP-BF533 EZ-KIT Lite Evaluation System Manual”: ADSP_BF533_EZ_KIT_Lite_Manual_Rev_3.0.pdf Veton Këpuska

  5. Push Button Enable Switch (SW9) • Positions: • 1 through 4 : disconnect the drivers associated with the push buttons from the PF pins of the processor. • 5 and 6 : are used to connect the transmit and receive frame syncs and clocks of SPORT0. This is important when the AD1836 video decoder and the processor are communicating in I2S mode. • Table 2-6 shows which PF is driven when the switch is in the default (ON) position. Veton Këpuska

  6. BF533 EZ-Kit Lite Circuit Schematics Veton Këpuska

  7. Lab 1 Details • Source code directory contains an example ADSP-BF533 project that shows how • Programmable Flag pins (FIO), • Interrupts, and • Timer can be configured in “C”. • It also demonstrates the access to the LEDs on the EZ-KIT Lite, which are connected to the on-board Flash. • Files contained in this directory: • BF533 Flags C.dpj VisualDSP++ project file • main.c C file containing the main program and variable declaration • Initialisation.c C file containing all initialization routines • ISRs.c C file containing the interrupt service routines for Timer and FIO • BF533 Flags.h C header file containing prototypes and macros • readme.txt this project description file Veton Këpuska

  8. Lab 1: Functional Description • This example demonstrates the initialization of the • External Bus Interface Unit - EBIU (asynchronous access), • Timer 0, • FIO pins, • Interrupts and the on-board Flash, which allows access to the six LEDs on the EZ-KIT. • The program simply turns on one LED and rotates the pattern left or right, depending on the state of an internal flag. • The switch connected to PF8 (SW4) can be used to toggle the state of this flag, which results in a change of direction of the moving light. Veton Këpuska

  9. Lab 1: Implementation Description • The main file calls: • FIO setup • Timer setup • EBIU setup • Flash setup • Interrupt configuration • Endless loop waiting for Timer interrupt or Flag interrupt Veton Këpuska

  10. Lab 1. Code Walk Through #include "BF533 Flags.h" #include "ccblkfn.h" #include "sysreg.h" //--------------------------------------------------------------------------// // Variables // //--------------------------------------------------------------------------// // flag indicating direction of moving light (toggled in FlagA ISR) short sLight_Move_Direction = 0; //--------------------------------------------------------------------------// // Function: main // //--------------------------------------------------------------------------// void main(void) { sysreg_write(reg_SYSCFG, 0x32); //Initialize System Configuration Register Init_Flags(); Init_Timers(); Init_EBIU(); Init_Flash(); Init_Interrupts(); while(1); } Veton Këpuska

  11. BF533 Flags.h See Table 1-5. Flash A Configuration Registers for Ports A and B in slide 14 #ifndef __BF533_FLAGS_DEFINED #define __BF533_FLAGS_DEFINED //--------------------------------------------------------------------------// // Header files // //--------------------------------------------------------------------------// #include <sys\exception.h> #include <cdefBF533.h> //--------------------------------------------------------------------------// // Symbolic constants // //--------------------------------------------------------------------------// // addresses for Port B in Flash A #define pFlashA_PortB_Dir (volatile unsigned char *)0x20270007 #define pFlashA_PortB_Data (volatile unsigned char *)0x20270005 //--------------------------------------------------------------------------// // Global variables // //--------------------------------------------------------------------------// extern short sLight_Move_Direction; //--------------------------------------------------------------------------// // Prototypes // //--------------------------------------------------------------------------// // in file Initialization.c void Init_Flags(void); void Init_Timers(void); void Init_EBIU(void); void Init_Flash(void); void Init_Interrupts(void); // in file ISRs.c EX_INTERRUPT_HANDLER(Timer0_ISR); EX_INTERRUPT_HANDLER(FlagA_ISR); #endif //__BF533_FLAGS_DEFINED Veton Këpuska

  12. Lab 1: Note • Make sure that switch SW9 pin1 is turned on (connects switch SW7 to pin PF8) 2 4 6 1 3 5 Veton Këpuska

  13. LED Interface

  14. How to “configure” the flash memory to control the LEDs Parallel interfaces present on the FLASH memory chips Veton Këpuska

  15. Flash General-Purpose IO • General-purpose IO signals are controlled by means of setting appropriate registers of the flash A or flash B. • These registers are mapped into the processor’s address space, as shown in the Table below (ADSP-BF533 EZ-KIT Lite Evaluation System Manual – Flash Memory) Veton Këpuska

  16. Flash General-Purpose IO • Flash device IO pins are arranged as 8-bit ports labeled A through G. • There is a set of 8-bit registers associated with each port. These registers are used for: • Direction, • Data In, and • Data Out. Note that the Direction and Data Out registers are cleared to all zeros at power-up or hardware reset. • The Direction register controls IO pins direction. This is a 8-bit read-write register. • When a bit is 0, a corresponding pin functions as an input. • When the bit is 1, a corresponding pin is an output. • The Data In register allows reading the status of port’s pins. This is a 8-bit read-only register. • The Data Out register allows clearing an output pin to 0 or setting it to 1. This is a 8-bit read-write register. • The ADSP-BF533 EZ-KIT Lite board employs only flash A and flash B ports A and B. Table 1-5 and Table 1-6 provide configuration register addresses for flash A and flash B, respectively (only ports A and B are listed in the next slide). • The following bits connect to the expansion board connector. • Flash A: port A bits 7 and 6, as well as port B bits 7 and 6 • Flash B: port A bits 7–0 Veton Këpuska

  17. Flash A & B Configuration Registers for Ports A and B. • Table 1-5. Flash A Configuration Registers for Ports A and B • Table 1-6. Flash B Configuration Registers for Ports A and B Veton Këpuska

  18. IO Assignments for Port A and Port B • Table 1-7 Flash A Port A Controls. • PPI – Parallel Peripheral Interface & Associated Configuration Registers. Veton Këpuska

  19. IO Assignments for Port A and Port B • Table 1-8 Flash A Port B Controls. Veton Këpuska

  20. User LEDs (LED4-9) • Six LEDs connect to six general-purpose IO pins of the flash memory (U5). • The LEDs are active high and are lit by writing a 1 to the correct memory address in the flash memory. Veton Këpuska

  21. BF533 Interface to PFI/PFs LED(6) EBIU PFI/PFs Veton Këpuska

  22. FIO Setup FIO setup Timer setup EBIU setup Flash setup Interrupt configuration Endless loop waiting for Timer interrupt or Flag interrupt

  23. Initialization.c #include "BF533 Flags.h" //--------------------------------------------------------------------------// // Function: Init_Flags // // // // Parameters: None // // // // Return: None // // // // Description: This function configures PF8 as input for edge sensitive // // interrupt generation. // // The switch connected to PF8 (SW4) can be used to change the // // direction of the moving light. // //--------------------------------------------------------------------------// void Init_Flags(void) { *pFIO_INEN = 0x0100; *pFIO_DIR = 0x0000; *pFIO_EDGE = 0x0100; *pFIO_MASKA_D = 0x0100; } This value programs PF8 pin. See BF533 HRM or slide 25for additional information. This reset value makes all pins as inputs.See BF533 HRM or slide 26for additional information This value sets PF8 pin to be EDGE sensitiveSee BF533 HRM or slide 28for additional information This value enables PF8 pin to accepts interrupts.See BF533 HRM or slide 30 for additional information Veton Këpuska

  24. Programmable Flags PFI/PFs • The processor supports 16 bidirectional programmable flags (PFx) or general-purpose I/O pins, PF[15:0]. • Each pin can be individually configured as either an input or an output by using the Flag Direction register (FIO_DIR). • When configured as output: • the Flag Data register (FIO_FLAG_D) can be directly written to specify the state of all PFx pins. • the state written to the • Flag Set (FIO_FLAG_S), • Flag Clear (FIO_FLAG_C), and • Flag Toggle (FIO_FLAG_T) registers determines the state driven by the output PFx pin. • Regardless of how the pins are configured, as an input or an output, reading any of these registers: • FIO_FLAG_D, • FIO_FLAG_S, • FIO_FLAG_C, or • FIO_FLAG_T returns the state of each pin. • They can be enabled via bits in Flag Input Enable register (FIO_INEN) • Input buffer associated with the PF flags is disabled by default. The Flag Input Enable register (FIO_INEN) is used to enable them. Veton Këpuska

  25. Flag Input Enable Register ADSP-BF533 Blackfin Processor Hardware Reference *pFIO_INEN = 0x0100 0000 0001 0000 0000 Veton Këpuska

  26. FIO_DIR Register • Each pin, PF[15:0], can be individually configured as either an input or an output by using the Flag Direction register (FIO_DIR) • The Flag Direction register (FIO_DIR) is a read-write register. • Each bit position corresponds to a PFx pin. • A logic 1 configures a PFx pin as an output, driving the state contained in the FIO_FLAG_D register. • A logic 0 configures a PFx pin as an input. The reset value of this register is 0x0000, making all PF pins inputs upon reset. • ⓘ Note when using the PFx pin as an input, the corresponding bit should also be set in the Flag Input Enable register. *pFIO_DIR = 0x0000 0000 0000 0000 0000 Veton Këpuska

  27. Programming PFx to generate an interrupt • Each PFx pin can be configured to generate an interrupt. • When a PFx pin is configured as an input, an interrupt can be generated according to the state of the pin, either • high or low • an edge transition (low to high or high to low), or • on both edge transitions (low to high and high to low). • Input sensitivity is defined on a per-bit basis by • the Flag Polarity register (FIO_POLAR), • the Flag Interrupt Sensitivity register (FIO_EDGE) and • The Flag Set on Both Edges register (FIO_BOTH). • Input polarity is defined on a per-bit basis by • the Flag Polarity register. • When • the PFx inputs are enabled and • a PFx pin is configured as an output, enabling interrupts for the pin allows an interrupt to be generated by setting the PFx pin. Veton Këpuska

  28. FIO_EDGE: Flag Interrupt Sensitivity Register *pFIO_EDGE = 0x0100 0000 0001 0000 0000 Veton Këpuska

  29. FIO_MASKx_D, FIO_MASKx_C,FIO_MASKx_S, FIO_MASKx_T, • Both Flag Interrupt A and Flag Interrupt B are supported by a set of four dedicated registers: • Flag Mask Interrupt Data register • Flag Mask Interrupt Set register • Flag Mask Interrupt Clear register • Flag Interrupt Toggle register • The Flag Mask Interrupt registers: • FIO_MASKA_D, FIO_MASKA_S, FIO_MASKA_C, FIO_MASKA_T, and • FIO_MASKB_D, FIO_MASKB_S, FIO_MASKB_C, FIO_MASKB_T are implemented as complementary pairs of: • Data “D”, write-1-to-set “S”, write-1-to-clear “C”, and write-1-to-toggle “T” registers. • This implementation provides the ability to: • enable or disable a PFx pin to act as a processor interrupt without requiring read-modify-write accesses—or to • directly specify the mask value with the data register. Veton Këpuska

  30. FIO_MASKA_D Register to Enable Interrupt *pFIO_MASKA_D = 0x0100 0000 0001 0000 0000 Veton Këpuska

  31. Initialization.c #include "BF533 Flags.h" //--------------------------------------------------------------------------// // Function: Init_Flags // // // // Parameters: None // // // // Return: None // // // // Description: This function configures PF8 as input for edge sensitive // // interrupt generation. // // The switch connected to PF8 (SW4) can be used to change the // // direction of the moving light. // //--------------------------------------------------------------------------// void Init_Flags(void) { *pFIO_INEN = 0x0100; *pFIO_DIR = 0x0000; *pFIO_EDGE = 0x0100; *pFIO_MASKA_D = 0x0100; } This value programs PF8 pin. See BF533 HRM or slide 25for additional information. This reset value makes all pins as inputs.See BF533 HRM or slide 26for additional information This value sets PF8 pin to be EDGE sensitiveSee BF533 HRM or slide 28for additional information This value enables PF8 pin to accepts interrupts.See BF533 HRM or slide 30 for additional information Veton Këpuska

  32. Timer Set Up FIO setup Timer setup EBIU setup Flash setup Interrupt configuration Endless loop waiting for Timer interrupt or Flag interrupt

  33. Timer Setup • The processor features • three identical 32-bit general-purpose timers, a • core timer, and a • watchdog timer. • The general-purpose timers can be individually configured in any of three modes: • Pulse Width Modulation (PWM_OUT) mode • Pulse Width Count and Capture (WDTH_CAP) mode • External Event (EXT_CLK) mode • The core timer is available to generate periodic interrupts for a variety of system timing functions. • The watchdog timer can be used to implement a software watchdog function. A software watchdog can improve system availability by generating an event to the Blackfin processor core if the timer expires before being updated by software. Veton Këpuska

  34. Initialization.c //--------------------------------------------------------------------------// // Function: Init_Timers // // // // Parameters: None // // // // Return: None // // // // Description: This function initialises Timer0 for PWM mode. // // It is used as reference for the 'shift-clock'. // //--------------------------------------------------------------------------// void Init_Timers(void) { *pTIMER0_CONFIG = 0x0019; *pTIMER0_PERIOD = 0x00800000; *pTIMER0_WIDTH = 0x00400000; *pTIMER_ENABLE = 0x0001; } Veton Këpuska

  35. General-Purpose Timer • Each general-purpose timer has one dedicated bidirectional chip pin, TMRx. • This pin functions as: • an output pin in the PWM_OUT mode and as • an input pin in the WDTH_CAP and EXT_CLK modes. • To provide these functions, each timer has (4) four 32 bit registers. • Timer Configuration (TIMERx_CONFIG) registers • Timer Counter (TIMERx_COUNTER) registers • Timer Period (TIMERx_PERIOD) registers • Timer Pulse Width (TIMERx_WIDTH) registers Veton Këpuska

  36. When clocked internally, the clock source is the processor’s peripheral clock (SCLK). Assuming the peripheral clock is running at 133 MHz, the maximum period for the timer count is ((232-1) / 133 MHz) = 32.2 seconds. Default SCLK clock rate is 54 MHz. For more info see: PLL_CTL & PLL_DIV registers. Timer Block Diagram Veton Këpuska

  37. Timer Control – TIMER_ENABLE & TIMER_DISABLE • The Timer Enable (TIMER_ENABLE) register can be used to enable all three timers simultaneously. • The register contains three “write-1-to-set” control bits, one for each timer. • Correspondingly, the Timer Disable (TIMER_DISABLE) register contains three “write-1-to-clear” control bits to allow simultaneous or independent disabling of the three timers. • Either the Timer Enable or the Timer Disable register can be read back to check the enable status of the timers. • A “1” indicates that the corresponding timer is enabled. • The timer starts counting three SCLK cycles after the TIMENx bit is set. Veton Këpuska

  38. Timer Control: TIMER_STATUS • The Timer Status (TIMER_STATUS) register contains • an Interrupt Latch bit (TIMILx) and • an Overflow/Error Indicator bit (TOVF_ERRx) for each timer. • These sticky bits are set by the timer hardware and may be polled by software. • They need to be cleared by software explicitly, by writing a “1” to the corresponding bit. Veton Këpuska

  39. Timer Configuration: TIMERx_CONFIG • To enable a timer’s interrupts, • Set the IRQ_ENA bit in the timer’s Configuration (TIMERx_CONFIG) register, and • With the IRQ_ENA bit cleared, the timer does not set its Timer Interrupt latch (TIMILx) bits. • Unmask the timer’s interrupt by setting the corresponding bits of the • IMASK and • SIC_IMASK registers. • To poll the TIMILx bits without permitting a timer interrupt, programs can set the IRQ_ENA bit while leaving the timer’s interrupt masked. Veton Këpuska

  40. Timer Configuration • With interrupts enabled, • Make sure that the interrupt service routine (ISR) clears the TIMILx latch before the RTI instruction, to ensure that the interrupt is not reissued. • To make sure that no timer event is missed, the latch should be reset at the very beginning of the interrupt routine when in External Clock (EXT_CLK) mode. Veton Këpuska

  41. Timer Registers • Each timer provides four registers: • TIMERx_CONFIG[15:0] – Timer Configuration register • TIMERx_WIDTH[31:0] – Timer Pulse Width register • TIMERx_PERIOD[31:0] – Timer Period register • TIMERx_COUNTER[31:0] – Timer Counter register • Three registers are shared between the three timers: • TIMER_ENABLE[15:0] – Timer Enable register • TIMER_DISABLE[15:0] – Timer Disable register • TIMER_STATUS[15:0] – Timer Status register • The size of accesses is enforced. • A 32-bit access to a Timer Configuration register (16-bit register) or • a 16-bit access to a • Timer Pulse Width, • Timer Period, or • Timer Counter registers • (32-bit registers) results in a Memory-Mapped Register (MMR) error. • Both 16- and 32-bit accesses (reads) are allowed for the • Timer Enable, • Timer Disable, and • Timer Status registers. • On a 32-bit read, the upper word returns all 0s. Veton Këpuska

  42. Initialization.c //--------------------------------------------------------------------------// // Function: Init_Timers // // // // Parameters: None // // // // Return: None // // // // Description: This function initialises Timer0 for PWM mode. // // It is used as reference for the 'shift-clock'. // //--------------------------------------------------------------------------// void Init_Timers(void) { *pTIMER0_CONFIG = 0x0019; *pTIMER0_PERIOD = 0x00800000; *pTIMER0_WIDTH = 0x00400000; *pTIMER_ENABLE = 0x0001; } TIMER0_CONFIG REGISTER INFO Veton Këpuska

  43. Timer Configuration Registers 0x0019 = 0000 0000 0001 1001 PWM_OUT PERIOD_CNT IRQ_ENA GO BACK Veton Këpuska

  44. Initialization.c //--------------------------------------------------------------------------// // Function: Init_Timers // // // // Parameters: None // // // // Return: None // // // // Description: This function initialises Timer0 for PWM mode. // // It is used as reference for the 'shift-clock'. // //--------------------------------------------------------------------------// void Init_Timers(void) { *pTIMER0_CONFIG = 0x0019; *pTIMER0_PERIOD = 0x00800000; *pTIMER0_WIDTH = 0x00400000; *pTIMER_ENABLE = 0x0001; } TIMER0_PERIOD REGISTER INFO Veton Këpuska

  45. TIMERx_PERIOD and TIMERx_WIDTH Registers • Usage of the Timer Period register (TIMERx_PERIOD) and the Timer Pulse Width register (TIMERx_WIDTH) varies depending on the mode of the timer: • In Pulse Width Modulation mode (PWM_OUT), both the Timer Period and Timer Pulse Width register values can be updated “on-the-fly” since the Timer Period and Timer Pulse Width (duty cycle) register values change simultaneously. • In Pulse Width and Period Capture mode (WDTH_CAP), the Timer Period and Timer Pulse Width buffer values are captured at the appropriate time. • The Timer Period and Timer Pulse Width registers are then updated simultaneously from their respective buffers. • Both registers are read-only in this mode. • In External Event Capture mode (EXT_CLK), the Timer Period register is writable and can be updated “on-the-fly.” The Timer Pulse Width register is not used. Veton Këpuska

  46. Timer Period Registers 0x00800000 = 0000 0000 1000 0000 0000 0000 0000 0000 = 223 = 83688608 If fSCLK = 133 MHz ⇒ N/fSCLK = 223 / 133 MHz ≈ 0.06 sec Default fSCLK = 56 MHz ⇒ 223 / 56 MHz ≈ 0.15 sec Veton Këpuska

  47. Initialization.c //--------------------------------------------------------------------------// // Function: Init_Timers // // // // Parameters: None // // // // Return: None // // // // Description: This function initialises Timer0 for PWM mode. // // It is used as reference for the 'shift-clock'. // //--------------------------------------------------------------------------// void Init_Timers(void) { *pTIMER0_CONFIG = 0x0019; *pTIMER0_PERIOD = 0x00800000; *pTIMER0_WIDTH = 0x00400000; *pTIMER_ENABLE = 0x0001; } TIMER0_WIDTH REGISTER INFO Veton Këpuska

  48. Timer-Width Registers • Timer Width Register specifies the duty cycle of the cycle. When Timer Width register is set to Timer Period/2 value the duty cycle is 50%. 0x00400000 = 0000 0000 0100 0000 0000 0000 0000 0000 = 222 = 4194304 Veton Këpuska

  49. Initialization.c //--------------------------------------------------------------------------// // Function: Init_Timers // // // // Parameters: None // // // // Return: None // // // // Description: This function initialises Timer0 for PWM mode. // // It is used as reference for the 'shift-clock'. // //--------------------------------------------------------------------------// void Init_Timers(void) { *pTIMER0_CONFIG = 0x0019; *pTIMER0_PERIOD = 0x00800000; *pTIMER0_WIDTH = 0x00400000; *pTIMER_ENABLE = 0x0001; } TIMER_ENABLE Veton Këpuska

  50. Timer Enable Enabling Timer0 0x0001 = 0000 0000 0000 0001 Veton Këpuska

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