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Team Glide Design Review Documents

Team Glide Design Review Documents. Graham Linn Srija Pidaparthy Marc Miyaki Submitted 5 Dec 06. Summary of Contents. System Block Diagram High level overview of entire project. System Schematic B2Logic layout showing how each part is connected. MOSIS Chip Information

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Team Glide Design Review Documents

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  1. Team Glide Design Review Documents Graham Linn Srija Pidaparthy Marc Miyaki Submitted 5 Dec 06

  2. Summary of Contents • System Block Diagram • High level overview of entire project. • System Schematic • B2Logic layout showing how each part is connected. • MOSIS Chip Information • Finite state machine diagram • State table • Excitation & Output equations (created using ABEL) • Schematic (presented in B2Logic) • Simulation trace (from B2Logic) • Off-MOSIS Logic • Finite state machine diagram for RCD.CKT and ACK Generator • B2Logic Schematics of components external to MOSIS chip • Simulation trace of each component • AC Analysis • Setup and Hold times for MOSIS and Off-MOSIS Logic • Power Analysis • Power Consumption for each component • DC Analysis • High/low voltage & current values for dissimilar parts (MS Excel Spreadsheet) University of Portland School of Engineering

  3. System Block Diagram *Double click to see item in more detail (Visio 2003 required) University of Portland School of Engineering

  4. System Schematic University of Portland School of Engineering

  5. MOSIS State Diagram *Double click to see item in more detail (Visio 2003 required) University of Portland School of Engineering

  6. MOSIS State Table • Please open this excel file University of Portland School of Engineering

  7. MOSIS Equations • Please open this text document to view excitation and output equations University of Portland School of Engineering

  8. MOSIS Chip Schematic Rev 22 Nov 06 University of Portland School of Engineering

  9. PLD.ckt University of Portland School of Engineering

  10. RCD.ckt State Diagram *Double click to see item in more detail (Visio 2003 required) University of Portland School of Engineering

  11. RCD.ckt University of Portland School of Engineering

  12. RCD Trace *since input is always VCC, setup and hold times are always met University of Portland School of Engineering

  13. CD.ckt University of Portland School of Engineering

  14. CD.Ckt Trace thold = 20 ns *tsetup is 0 because input is always VCC to D-Flip Flop and Counters University of Portland School of Engineering

  15. ACK State Diagram Rev 2 Dec 06 *Double click to see item in more detail (Visio 2003 required) University of Portland School of Engineering

  16. ACK.ckt University of Portland School of Engineering

  17. ACK Trace tsetup=20ns thold=50 ns University of Portland School of Engineering

  18. Serial to Parallel University of Portland School of Engineering

  19. Serial to Parallel Trace thold=16 ns tsetup=20 ns University of Portland School of Engineering

  20. BTNCONV.ckt University of Portland School of Engineering

  21. VMUX.ckt University of Portland School of Engineering

  22. AC Analysis • Clock will be 1 kHz University of Portland School of Engineering

  23. Power Analysis University of Portland School of Engineering

  24. DC Analysis • Please open this file to view DC Analysis University of Portland School of Engineering

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