TOPIC : Memory modeling

# TOPIC : Memory modeling

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## TOPIC : Memory modeling

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1. TOPIC : Memory modeling Module 4.1 : Memory modeling in Verilog

2. Memories • In digital simulation, one often needs to model register files, RAMs, and ROMs. Memories are modeled in Verilog simply as an array of registers. • Each element of the array is known as a word. Each word can be one or more bits. It is important to differentiate between n 1-bit registers and one n-bit register. • A particular word in memory is obtained by using the address as a memory array subscript.

3. Memory • Different types and sizes of memory, register file, stack, etc., can be formed by extending the vector concept. Thus the decleration Reg [15:0] memory[511:0]; • Declared an array called memory; it has 512 locations. Each location is 16 bits wide. The value of any chosen location can be assigned to a selected register or vice-versa; this constitutes memory reading or writing. The index used to refer a memory location can be a number or an algebraic expression which reduces to an integral value – positive, zero, or negative. • B = mem[3] //data stored at mem[3] is assigned to B

4. Memory decleration • Reg mem1bit[0:1023] //Memory mem1bit 1k 1-bit words. • Reg [7:0] membyte[0:1023]; //Memory membyte with 1k 8-bit words (bytes) • Membyte [511] //Fetches 1 byte word address is 511.