Background

1. Background • Program must be brought into memory and placed within a process for it to be run. • Input queue – collection of processes on the disk that are waiting to be brought into memory to run the program. • User programs go through several steps before being run.

2. Binding of Instructions and Data to Memory • Compile time: If memory location known a priori, absolute code can be generated; must recompile code if starting location changes. • Load time: Must generate relocatable code if memory location is not known at compile time.

3. Execution time: Binding delayed until run time if the process can be moved during its execution from one memory segment to another. Need hardware support for address maps (e.g., base and limit registers).

4. Logical vs. Physical Address Space • The concept of a logical address space that is bound to a separate physicaladdress space is central to proper memory management. • Logical address – generated by the CPU; also referred to as virtual address. • Physical address – address seen by the memory unit. • Logical and physical addresses are the same in compile-time and load-time address-binding schemes; logical (virtual) and physical addresses differ in execution-time address-binding scheme.

5. Memory-Management Unit (MMU) • Hardware device that maps virtual to physical address. • In MMU scheme, the value in the relocation register is added to every address generated by a user process at the time it is sent to memory. • The user program deals with logical addresses; it never sees the real physical addresses.

6. Dynamic relocation using a relocation register

7. Dynamic loading to reduce memory requirements • Routine is not loaded until it is called • Better memory-space utilization; unused routine is never loaded. • Useful when large amounts of code are needed to handle infrequently occurring cases.

8. Dynamic Linking • Linking postponed until execution time. • Small piece of code, stub, used to locate the appropriate memory-resident library routine. • Stub replaces itself with the address of the routine, and executes the routine. • Operating system needed to check if routine is in processes’ memory address. • Dynamic linking is particularly useful for libraries.

9. Overlays • Keep in memory only those instructions and data that are needed at any given time. • Needed when process is larger than amount of memory allocated to it. • Implemented by user, no special support needed from operating system, programming design of overlay structure is complex

10. Swapping • A process can be swapped temporarily out of memory to a backing store, and then brought back into memory for continued execution. • Backing store – fast disk large enough to accommodate copies of all memory images for all users; must provide direct access to these memory images.

11. Schematic View of Swapping

12. Contiguous Allocation • Main memory usually into two partitions: • Resident operating system, usually held in low memory with interrupt vector. • User processes then held in high memory. • Single-partition allocation • Relocation-register scheme used to protect user processes from each other, and from changing operating-system code and data. • Relocation register contains value of smallest physical address; limit register contains range of logical addresses – each logical address must be less than the limit register.

13. Hardware Support for Relocation and Limit Registers

14. Contiguous Allocation (Cont.) • Multiple-partition allocation • Hole – block of available memory; holes of various size are scattered throughout memory. • When a process arrives, it is allocated memory from a hole large enough to accommodate it. • Operating system maintains information about:a) allocated partitions b) free partitions (hole)

15. OS process 5 process 8 process 2

16. OS process 5 process 2 OS process 5 process 8 process 2

17. OS OS process 5 process 5 process 9 process 2 process 2 OS process 5 process 8 process 2

18. OS OS OS process 5 process 5 process 5 process 9 process 9 process 10 process 2 process 2 process 2 OS process 5 process 8 process 2

19. Fragmentation • External Fragmentation – total memory space exists to satisfy a request, but it is not contiguous. • Internal Fragmentation – allocated memory may be slightly larger than requested memory; this size difference is memory internal to a partition, but not being used.

20. Fragmentation • Reduce external fragmentation by compaction • Shuffle memory contents to place all free memory together in one large block. • Compaction is possible only if relocation is dynamic, and is done at execution time.

21. Paging • Logical address space of a process can be noncontiguous; process is allocated physical memory whenever the latter is available. • Divide physical memory into fixed-sized blocks called frames (size is power of 2, between 512 bytes and 16MB bytes). • Divide logical memory (i.e., memory addresses generated by CPU) into blocks of same size called pages.

22. Paging • OS keeps track of all free frames. • To run a program of size n pages, need to find n free frames and load program. • Set up a page table to translate logical to physical addresses. • Fragmentation?

23. Paging • OS keeps track of all free frames. • To run a program of size n pages, need to find n free frames and load program. • Set up a page table to translate logical to physical addresses. • Fragmentation? Possible to have internal fragmentation, not external.

24. Address Translation Scheme • Address generated by CPU is divided into: • Page number(p) – used as an index into a pagetable which contains base address of each page in physical memory. • Page offset(d) – concatenated with base address to determine the physical memory address that is sent to the memory unit.

25. Paging System Example • Memory consists of 32 Page Frames. • Pages are 1024 bytes. • How many bits in physical address?

26. Paging System Example • Memory consists of 32 Page Frames. • Pages are 1024 bytes. • How many bits in physical address? • 1) How many bits needed to access all pages?

27. Paging System Example • Memory consists of 32 Page Frames. • Pages are 1024 bytes. • How many bits in physical address? • 1) How many bits needed to access all pages? 5: 2^5 = 32.

28. Paging System Example • Memory consists of 32 Page Frames. • Pages are 1024 bytes. • How many bits in physical address? • 1) How many bits needed to access all pages? 5: 2^5 = 32. • 2) How many bits needed to access all memory locations within a page?

29. Paging System Example • Memory consists of 32 Page Frames. • Pages are 1024 bytes. • How many bits in physical address? • 1) How many bits needed to access all pages? • 5: 2^5 = 32. • 2) How many bits needed to access all memory locations within a page? • 10: 2^10 = 1024. • This machine using 15 bit addresses.

30. Paging System Example • Compiler generates relative (or logical) addresses. • Relative to the beginning of the program. • Same number of bits in physical and logical addresses. • Assume process P0 consists of 5096 bytes. • Consider variable located at relative address 1029. 000010000000101

31. Physical Memory Process P0: 5096 bytes. How many pages in logical address space? 0 1 2 29 30 31

32. Physical Memory Process P0: 5096 bytes. How many pages in logical address space? 5 0 1 2 29 30 31

33. Physical Memory Process P0: 5096 bytes. Logical Address space. 0 1 2 0 1 Contiguous 2 29 3 30 31 4

34. Process P0: 5096 bytes. Logical Address space. What is page number and offset within page for logical address 1029? 0 1 Contiguous 2 3 4

35. Process P0: 5096 bytes. Logical Address space. What is page number and offset within page for logical address 1029? Pages are 1024 bytes, so 1029 falls in logical page 1 with offset of 5. 0 1 2 Contiguous 3 4

36. Physical Memory Process P0: 5096 bytes. Logical Address space. 0 1 2 P0.0 1 0 1 2 29 3 30 31 4

37. Physical Memory Process P0s logical address space. 0 1 2 P0.0 1 0 P0.1 1 3 2 29 3 30 31 4

38. Physical Memory Process P0: 5096 bytes. Logical Address space. 0 1 2 P0.2 P0.0 1 0 3 P0.1 1 3 2 0 29 3 30 31 4

39. Physical Memory Process P0: 5096 bytes. Logical Address space. 0 1 2 P0.2 P0.0 1 0 3 P0.1 1 3 2 0 29 3 30 P0.3 30 31 4

40. 0 1 2 P0.2 P0.0 P0.4 3 P0.1 29 P0.3 30 31 Physical Memory Process P0: 5096 bytes. Logical Address space. 1 0 1 3 2 0 3 30 4 2

41. 0 1 2 P0.2 P0.0 P0.4 1 0 3 P0.1 1 3 2 0 29 3 30 P0.3 30 31 4 2 Physical Memory This is the Page Table for process P0. Maps logical pages to physical pages.

42. 0 1 2 P0.2 P0.0 P0.4 3 P0.1 29 P0.3 30 31 Physical Memory • Frame Physical Ad. • 0 0 - 1023 • 1 1024 - 2047 • 2048 – 3071 • 3072 – 4095 Logical address 1029 stored in physical location 3077.

43. 1 0 1 3 2 0 3 30 4 2 Page Table for Process P0: CPU generates Logical Address 1029. 000010000000101 Address broken into page number:offset within page.

44. 1 0 1 3 2 0 3 30 4 2 Page Table for Process P0 000010000000101 Page#Offset within page.

45. 1 0 1 3 2 0 3 30 4 2 Page Table for Process P0 000010000000101 Page#Offset within page. How it works: Page number used as index into page table.

46. 1 0 1 3 2 0 3 30 4 2 Index into Page Table 00001 00001 0000000101 Page Offset

47. 1 0 1 3 2 0 3 30 4 2 Index into Page Table 00001 000110000000101 = 3077 Physical page number concatenated with offset is physical address.

48. Paging Examples Assume a page size of 1K and a 15-bit logical address space. How many pages are in the system?

49. Paging Examples Assume a page size of 1K and a 15-bit logical address space. How many pages are in the system? How many bits are required to address each byte within a 1024-byte page?

50. Paging Examples Assume a page size of 1K and a 15-bit logical address space. How many pages are in the system? How many bits are required to address each byte within a 1024-byte page? 10 (2^10 = 1024). This leaves 5 bits for page number. So, How many pages are in the system?