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Group M3 Jacob Thomas Nick Marwaha Darren Shultz Craig LeVan Project Manager: Zachary Menegakis

Group M3 Jacob Thomas Nick Marwaha Darren Shultz Craig LeVan Project Manager: Zachary Menegakis. DSP 'Swiss Army Knife'. MILESTONE 3 Size estimates/Floorplan. February 2,2005. Overall Project Objective: General purpose Digital Signal Processing chip. STATUS.

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Group M3 Jacob Thomas Nick Marwaha Darren Shultz Craig LeVan Project Manager: Zachary Menegakis

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  1. Group M3 Jacob Thomas Nick Marwaha Darren Shultz Craig LeVan Project Manager: Zachary Menegakis DSP 'Swiss Army Knife' MILESTONE 3 Size estimates/Floorplan February 2,2005 Overall Project Objective: General purpose Digital Signal Processing chip

  2. STATUS • Design Proposal (Done) • Architecture (Done) • Size Estimates/Floorplan/Verilog (90%) • To Be Done • Structural Verilog Reengineering • Control Logic • Low-Level Modules • Schematic • Verification

  3. MARKETING UPDATE • How Does Our Circuit Fit Into the Bigger Picture? • Focus on Audio/Video Applications • Audio: • Digital Radios / MP3 Players (i.e. Motorola, Lucent, Texas Instruments) • Digital Music Synthesis / Sampling (i.e. Yamaha, Korg) • Noise Reduction (i.e. Dolby) • Video: • Comb Filter to separate color and brightness (i.e. Sony, Toshiba) • Others: • Motor Control Functions such as RPM (i.e. Ford, GE)

  4. MARKETING UPDATE cont Highlighted Areas Contain Many Instances of our Circuit Key Functions used: Integrators and Filters REUSE!!!!

  5. MARKETING UPDATE cont A Moving Averager Smoothes a Signal to Reduce Noise

  6. DESIGN DECISIONS • Finalized bit-width to 12-bit floating point • Based on CMU Research in Voice Recognition • Complexity => Our Applications in Audio and Video • 6-bit exponent, 5-bit fraction • Additional Precision cannot be discerned by humans • Reduces Power Consumption • Increased bit-width does not add to quality/versatility • Chip Applications would benefit from low power consumption • Size offers advantages of parallel processing to increase speed • Serial (software) vs. Parallel (hardware) operations

  7. DESIGN DECISIONS cont

  8. DESIGN DECISIONS cont

  9. FLOORPLAN Each block is approximately 100 * 100 with the exception of the possibly larger comb filter

  10. FLOORPLAN alternative

  11. POROSITY • STOLEN FROM W1 2004 (Thanks Myron & Bobby)

  12. SIZE ESTIMATES Adder: 5 * (200 + 200 + 100) = 2500 Mult: 7 * (900+200) = 8000 Div: 2 * (1000 + 200) = 2400 Fmult: 1 * (1200) = 1,200 Misc: (700 + 250) = 2,000 Registers: 83 * ~22 = 1,900 18,000 transistors

  13. VERILOG

  14. PROBLEMS & QUESTIONS • Determine Bit Width • Floorplan – Minimize Comb Filter or use Alternative? • Should Focus Be Area or Global Routing? • Structural Verilog • Fix Control Logic within Basic Blocks

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