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This lecture focuses on the application of Karnaugh Maps in simplifying logic circuits for home alarm systems. It details the design components, including inverters, AND gates, and OR gates, alongside their delay calculations. The presentation illustrates how to create an equivalent Karnaugh Map, emphasizing the importance of grouping bits according to the powers of two. Simplification techniques, including the use of don't-care conditions and ordered truth tables, are discussed to enhance the efficiency of logic design.
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Lecture 3 Karnaugh Map Chapter 2 Jack Ou, Ph.D.
Sum of Products Equation • Parts • 12 inverters • 3 2-input AND gates for each 4-input AND gate. Therefore, 24 2-input AND gates. • 7 2-input OR gates.
Delay Calculations • Parts • 12 inverters (1 TTL delay) • 3 2-input AND gates for each 4-input AND gate. Therefore, 24 2-input AND gates. • Each AND gate: 2 TTL delay • For each 4-input ANDN gate: 4 TTL delay • 7 2-input OR gates. • 2 TTL delay for each OR gate • 7 2-input OR gates (6 TTL delay) • Total delay: 6 TTL delay+4 TTL delay+1 TTL delay=11 TTL delay
Simplification Technique #1: Ordered the Truth Table using Gray Code Discontinuity disappears!
Simplified SoP • Parts: • Inverters: 4 inverters (1 TTL delay) • 4 3-input AND gates • Each 3-input AND gate requires 2 2-input AND gate: • 2 x4=8 2-input AND gate (4 TTL delay) • 3 2-input OR gate (4 TTL delay) • Maximum 9 TTL delay (4+4+1)
Move Don’t Care Bits Closer Together • Parts: • 1 inverter (1 delay) • 2 AND gates (2 delays) • 1 OR gate (2 delay) • 5 delay
Steps for Creating a Karnaugh Map • Create an Equivalent Karnaugh Map • Each circle must be around a power of two number of bits • It is not a problem if circles overlap
