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## EE 587 SoC Design & Test

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**EE 587SoC Design & Test**Partha Pande School of EECS Washington State University pande@eecs.wsu.edu**Iavg**v t Technology Scaling Effects • At 0.5um and above: Simple capacitance • At 0.35um and below: Resistance • At 0.18um and below : Coupling Capacitance • At 0.10um and below: Inductance .....**Interconnect Capacitance Profiles**• Total capacitance can be decomposed into three components: • Area capacitance • Lateral capacitance • Fringe capacitance V e r t i c a l s p a c i n g b e t w e e n H c o n d u c t o r s T S H e i g h t a b o e v S u b s t r a t e Horizontal spacing between conductors W H Ctotal = Carea + Clateral + Cfringe**Wire Dimensions**• T=wire thickness, H=vertical wire separation, S=horizontal wire separation, W=wire width, L=wire length • T and H are fixed parameters based on the fabrication process • W, S and L are under the designer’s control**Computation of Area Capacitances**• Area capacitance per unit length can be simply calculated using: Metal 2 Ca H W Metal 1 Ca Ca= ox W = 0.035fF/um (W/H) H**Computation of Lateral Capacitances**• Lateral capacitance per unit length for closely spaced wires can be calculated using: • For widely spaced wires, CL drops off as 1/S Metal 2 Closely spaced wires S T Metal 1 CL CL CL= ox T = 0.035fF/um (T/S) s**Computation of Fringe Capacitances**Metal 2 Ca Widely separated wires H Cf Cf T Metal 1 Ca For widely spaced conductors**Computation of Total Capacitances**• For closely spaced wires, assume fringe is small • For widely spaced wires, assume lateral is small • For medium spaced wires, Cf and CL will both exist and vary with S Metal 2 Cf Ca Cf T Metal 1 CL CL Ca Ctotal= 2Ca + 2CL = 0.2fF/um Ctotal= 2Ca + 2Cf = 0.2fF/um**Wire Capacitance Trend**Inter-metal capacitance**Coupling Effects**• New model of interconnect • Each driver connected to A,B,C or D can act as aggressor • Coupling capacitance could inject noise or affect delay A B C D Agressor CC Victim Cg**First-Order Delay Analysis**• If aggressor is not switching • If aggressor switches in same direction. • If aggressor switches in opposite direction: “Miller” factor • Multiplying factor ranges from 0 to 2 (Actual range is –1 to 3) Rup CC Rdn Cg Rdn Cg Rup V DD C C Rdn C g**Signal Integrity Effect on Timing**Net delay due to a single coupled aggressor net Net delay due to multiple coupled aggressor nets Victim net without coupling Victim net without coupling Victim net with coupling delay Victim net with coupling delay Aggressor net Aggressor nets Performance impact: 300 picosecond delay (3% of a clock cycle) Performance impact: over 2 nanosecond delay (20+% of a clock cycle)**First-order Noise Analysis**• Assume that aggressor and driver resistances are negligible • If V1 changes by VDD, what change V do we expect to see at the internal node in the worst case? • Produces results that are somewhat pessimistic Cc (V1 - V2) = CgV2 V1 Cc CcV1 Cc V1 V2 V2 = V2 = Cc + Cg Cc + Cg Cg CcVdd Looks like the feed through equation V2 = Cc + Cg**2nd-order Noise Analysis**How much noise is actually injected into the victim line by a voltage transition on the aggressor line? aggressor Cg Treat RC problem as a resistive divider: CC Vdd VO = Zdn VDD victim Cg Zdn + Zup VDD Rdn 1 + sCgRdn Zdn = Rup Zdn + Zup Rdn 1 + sCgRdn CC + (Rup + 1/sCc) Rdn sCc Cg = s2RupCcCg + s(Cc + CcRup/Rdn + Cg) + 1/Rdn**Capacitive Coupling**• What is the maximum value of spike? Depends on values of R,C • Worst case would be large Cc, small Cg, small Rup, large Rdn • Look at some limits: Vpeak < Vdd*Rdn/(Rdn+Rup) (set Cc infinite, Cg=0) Vpeak < Vdd*Cc/(Cc+Cg) (set Rup=0, Rdn infinite) • Voltage spike response depends on RC ratios • going up, time constant is RupCc • going down, time constant is Rdn(Cg + Cc) Rup VDD CC Rdn Cg Rdn*(Cg+Cc) < RupCc Amplitude based on resistor ratio Rdn*(Cg+Cc) > RupCc Amplitude based oncapacitance ratio**Wire Model of a Bus**For an inner wire the total bottom capacitance is For an outer wire**Signal Integrity Issues at FF’s**• What happens if a glitch occurs in a clock signal? • Flip-flop captures and propagates incorrect data • Could view any signal that, if glitched, could cause a logic upset as a “clock” signal • Need to space out clocks/signals or shield them Positive-Edge Triggered Flip-Flop D Q Clk Clk**Signal Integrity Issues at FF’s**• What happens if a glitch occurs in data signal? • Flip-flop captures and propagates incorrect data • Need to insure that data signal is stable during FF setup time • Shielding with stable signals or spacing is needed Positive-Edge Triggered Flip-Flop D Q Clk Clk**Reducing Coupling Capacitance**• Space out the signals as much as possible, but it cost area. (a) higher coupling cap./less area (b) lower coup. cap./ more area • Use Vdd and Gnd to shield wires wherever required (a) higher coupling cap./less area (b) higher tot. cap./ more area A B A B Vdd A B Gnd A B**Reducing Coupling Capacitance**• Copper and low-k dielectrics • try to reduce k from 3.9 to 2 • lower coupling caps • better electromigration reliability M5 via5 M4 via4 M3 via3 M2 via2 M1 cont Cu e1 Low-k Dielectrics e2 e2 e2 silicon e1 Multiple Levels of Metal**Crosstalk Avoidance through Coding**• A wire has maximum coupling if and only if it has a rising (falling) transition when both its neighboring wires have falling (rising) transitions.**Forbidden Pattern Codes**• Avoiding bit patterns 010 and 101 from every codeword . • However, encoding all bits at once using this is infeasible for large buses due to prohibitive complexity of the codec circuits. • Therefore, partial coding is employed, in which the bus is broken into sub-buses of smaller width which are encoded into sub channels. • These sub-channels are then combined in such a way so as to avoid crosstalk delay at their boundaries.**Forbidden Adjacent Boundary Pattern Condition**• codeword with 01 pattern does not transition to a codeword 10 pattern at the same bit boundary.**Forbidden Overlap Condition**• The codebook cannot have both 010 and 101 appearing centered around any bit position.**[3-0]**[4-0] [3-0] [4-0] [31-0] FOC 4-5 (7) FOC 4-5 (8) FOC 4-5 (1) FOC 4-5 (2) [39-0] Input Output [3-0] [4-0] [3-0] [4-0] Clock Reset Overall scheme**Hamming Codes**• For SEC Hamming code, 3 check bits are added to the 4 information bits**Dual Rail Code**• For a bus of k information bits, m=k+1 check bits need to be added • The k+1 check bits are defined as • Check bits for i= 0 to k-1 are a copy of the respective data bits, whereas check bit is a data parity bit**Codec**• Implementation of Coder & Decoder (Codec) is important • Area overhead • Extra energy dissipation • Reliability comes at a cost**Summary**• Crosstalk has serious effects on signal reliability in UDSM era • Only shielding or other traditional techniques are not sufficient • CAC is a promising solution • We need to consider area-power tradeoff