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Coniston 硬體線路說明 2006/09/04 RDEE3 PowerPoint Presentation
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Coniston 硬體線路說明 2006/09/04 RDEE3

Coniston 硬體線路說明 2006/09/04 RDEE3

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Coniston 硬體線路說明 2006/09/04 RDEE3

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  1. Coniston 硬體線路說明 2006/09/04 RDEE3

  2. Agenda • Basic concept • Block Diagram • Power up timing Block • Power up flowchart • Circuits Exploded Block • VGA portion

  3. Basic concept

  4. What is the Bus? • A data transmission channel between ICs . • Two types Bus – Parallel and serial Bus • How to debug Bus: • 每一種 Bus 都有自己的 protocol,傳輸資料時無法以示波器知道 Bus 現在在做什麼(一般以 LA 為工具). • 系統設計時就確保 Bus 是健全的, 所以……….. • 先找出那個 Bus 出問題. • 若整個 Bus 不動,先查 CLK, power (過 bead)及控制訊號. • 目視相關線路零件有無空焊,短路或錯料. • 以示波器直接掃瞄 Bus 有無短路,斷路. • 照 X ray.

  5. Parallel Bus D0 . . D64 A3 . . A16 ADS# DRDY# . . TRDY# D0 . . D64 A3 . . A16 ADS# DRDY# . . TRDY# Data Bus Address Bus Control Bus Clocks Parallel Bus 有 FSB, PCI, IDE, DDR, FDD, Parallel port

  6. Serial Bus Data CLK Data CLK Data/Address/Control Bus Serial Bus 有 DMI, PCIE, SATA, AC97, USB, IR,

  7. IC active sequence Power Clocks Power good Reset Some ICs complete Power good and Reset together ex. ICH

  8. What is +V?A, +V?, +V?S 電源插入時 +V?A 系統開機後 +V?A, +V?, +V?S 系統進入待命 +V?A, +V? 系統關機或進入休眠 +V?A

  9. Block Diagram

  10. Coniston Block Diagram

  11. Power up timing Block

  12. Power up timing Block Reset IC / DC +V3A/+V5A Charger • Adapter 2 +VBAT 1 Battery 3 +V3A/+V5A 4 ICH KBC 5 NB CPU Power button RSMRST# 6 SLP_S5/S4/S3 8 Clocks out 7 Clock-G Power IC IMVP_CKEN

  13. Power up timing Block Cont. Reset IC / DC +V3A/+V5A Charger 13 H_ADS# ICH KBC 11 NB 12 CPU PLT_RST# H_CPURST# 10 H_PWRGD 9 PWROK Power IC Clock-G

  14. Coniston power up timing

  15. Coniston power up timing cont.

  16. Coniston Power up timing cont.

  17. Power up flowchart

  18. Power Up FlowchartFirst Step – Power In +VBAT Adapter In 19V OR Battery In Charger Circuits U716 (sheet4) TI_BQ24721 +V5LA source +V3LA Source U32 (sheet6) TI_TPS51120 Reset IC U29 (sheet5) GMT_G680LT1 +VBAT +V5AUXON +V5LA +VBAT +V5A DC/DC(+V3A/+V5A) U32 (sheet6) TI_TPS51120 +V_RTC source D718 (sheet 39) BAT54C +V_RTC +V5AUXON +V3A KBC active U25 (sheet52) KBC1122 BIOS U1500 (sheet53) SST_39VF080 Access BIOS

  19. Power Up Flowchart2’th Step – Push power button +VGAVCC U30 (sheet9) Ti_TPS51124RGER This page shows power sequence between power button to all system powers up +V3A KBC1122 U25 (sheet52) 32.768KHz PWR_SWIN#_3 +V1.5S U707 (sheet8) Ti_TPS51124RGER +V1.5S_PWRGD RSMRST# +V5S Q52,Q53 (Sheet12) Q36 U27 (sheet10) GMT_G966 +V2.5S 32.768KHz +V3S SLP_S3#_3R ICH7 U708(sheet39~43) LOW_BAT# +V_RTC +V1.5S U718 (sheet10) GMT_G966 +V5S SLP_S5#_3R +V1.2S Q729 (sheet10) A04406 +V1.8S U30 (sheet9) Ti_TPS51124RGER +V1.8 U22(sheet10) GMT_G2997F6U +V0.9S SLP_S3#_3R M_VFER SLP_S5#_3R

  20. Power Up Flowchart3’th Step – CPU power up and Reset timing +VCC_CORE +VCCP U709(sheet7) ADI_ADP3207 +V1.5S_PWRGD U5 (sheet12) NC7W17 U707 (sheet8) Ti_TPS51124 PWR_GOOD_# IMVP_CKEN# SLP_S3#_3R MCH_GOOD VR_PWRGD_CK410 H_CPURST# U717 (sheet20) 945PM/GM CN712 (sheet14~17) CPU H_ADS# IMVP_CKEN# U28 (sheet13) ICS9LPR316 Clocks PLT_RST# VR_PWRGD_CK410 U7 (sheet7) NC7WZ17 U708 (sheet41) ICH7 PM_PWROK +V5AUXON H_PWRGD SLP_S3#_3R U25 (sheet52) KBC1122 SB_3S_VRMPWRGD

  21. Circuits Exploded Block

  22. Reset IC 開啟 +V3A/+V5A 的第一個訊號 thermal IC 過熱時會透過KBC 拉 low 關閉整個系統電源 (R1) +V5AUXON will declare DC/DC circuits to output +V3A/+V5A (R2) +VBAT (lo)= 7.59V = 1.245 X( R1+R2+R3) / (R2+R3) +VBAT (hi)= 8.27V = 1.245 X (R1+R2+R3) / R3 (R3) Page 5

  23. Another control logic for +V5AUXON Page 72 也就是說DC mode要等user按power Bottom才會將+V5A,+V3A打開 AC mode EC會自動將 +V5A, +V3A always 的電打開

  24. DC/DC +V3A, +V5A, +V5LA Page 6

  25. EC active 這是EC的Power Bottom訊號 這是Power Switch 的訊號 EC_PWRSW# is for KBC to power on ICH, In normal it will be high. RSMRST# is for KBC to reset ICH KBC 第一次 收到 PWR_SWIN#_3 low 時, 會把 RSMRST# 拉 high to reset ICH Make sure 32.768KHz is oscillating. Page 52

  26. 南橋要開電前的必要條件 Page 40 • RTC have to be oscillating(32.768KHz). • RTCRST# have to be high. • RSMRST# have to be inactive (high). • PWRBTN# have a trigger. • LOW_BAT#_3 have to be inactive (high). • If true, then ICH will issue SLP_S3#_3R / SLP_S4#_3R. Page 39

  27. 南橋會送出S3#,S5#的訊號去開啟系統 +V? +V?S 的電源 SLP_S3#_3R turn on +V?S powers SLP_S4#_3R turn on +V? powers Page 40

  28. 南橋會送出 SLP_S3/SLP_S4 去開啟系統所有需要的電源 電源概分兩種 : PWM & LDO. 但開電的必要條件都一樣 ~~ source power, enable pin 以下兩種線路都是 LDO type Source power Enable Pin Page10

  29. Power_Good訊號的產生與目的 確認CPU外的電源都已起穩定, 並準備去開 CPU powers. When All +V?S/+V? powers are ready, PWR_GOOD_3 will tie to high to turn on CPU powers (+VCCP and +VCC_CORE). Page 12

  30. 開啟+VCCP電源和MCH_GOOD的產生 PWR_GOOD_3 turn on +VCCP When +VCCP is ready, this DC circuits will issue MCH_GOOD to turn on +VCC_CORE. Page 54

  31. 開啟+VCC_CORE電源和VR_PWRGD_CK410 / IMVP_CKEN# 的產生 MCH_GOOD enable IMVP to generate +VCC_CORE When +VCC_CORE power is ready, VR_PWRGD_CK410 will go high to inform system that CPU powers are ready. When +VCC_CORE is ready, IMVP_CKEN# will go high to enable clock-G Page 7

  32. CLOCKs 的產生 PCI_STOP#_3 and CPU_STOP#_3 must be at high otherwise some clocks will be turned off. Turn on all clocks by IMVP_CKEN# Page 13

  33. Chipset’s power good 產生 當 CPU power 穩定時, 用 VR_PWRGD_ck410 經 delay線路產生 SB_3S_VRMPWRGD通知南橋及KBC – cpu 電源已穩定 為確保 clocks 已穩定送出, 所以再經一次 delay 送出 PM_PWROK 給南北橋 Page 7

  34. 南橋Power Good的來源 南橋收到這兩個power good 訊號後,會reset內部的邏輯線路,並發 H_PWRGD 告之CPU 電源控制部分已備妥. 接著發 PLT_RST# reset 北橋, 然後起動DMI 與 北橋溝通. Page 40

  35. RESET北橋 南橋會送PLT_RST#來Reset北橋 Page 18

  36. FSB BUS 的第一個訊號 ADS# 是 RESET CPU後的第一個系統訊號去和北橋溝通 Page 14

  37. DMI 的第一個訊號 這是北橋和南橋間的溝通訊號 Page 18

  38. ICH 與 KBC 間的 Bus - LPCLPC 的第一個訊號 量測FRAME#看 LPC是否有動作 Page 39

  39. 系統讀 FLASH ROM的第一個訊號 量測FLASH看系統是否有解到FLASH ROM的第一個位址 Page 53

  40. 希望這份資料對各位有幫助 如果有問題請電郵 Power Member • 謝宗翰 Shie.jung-han@inventec.com EE Member • 溫淑惠 Wen.Sophie@inventec.com • 范仁和 Fan.Jen-Ho@inventec.com 謝謝指教