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This study utilizes graph theory and visualization to analyze the fundamental resource needs of key algorithms, focusing on data locality, memory bandwidth, and latency tolerance. It explores concurrent functional unit usage and assembly language conversion for efficient algorithm execution.
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Algorithms • Use a combination of graph theory and visualization to understand fundamental resource requirements for key algorithms • How many concurrent functional units can be used (how far can we go with packing FPUs on a single chip?) • Data Locality (hierarchical data locality) • Memory bandwidth requirements • Latency tolerance (maximum load-to-use distance) • Dependency graph sources • Assembly language conversion (visualize register transfers & operational dependencies) • Modified GCC (create hybrid dataflow/control-flow graph) • Trace-driven address resolution (converts hybrid dataflow/control-flow graph into a pure dataflow graph)